OTBN Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	77.204us	1	1	100.00
V1	single_binary	otbn_single	1.067m	306.955us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	10.000s	18.320us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	22.263us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	60.739us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	22.798us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	62.224us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	22.263us	20	20	100.00
		otbn_csr_aliasing	6.000s	22.798us	5	5	100.00
V1	mem_walk	otbn_mem_walk	52.000s	4.786ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	528.056us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	44.000s	164.435us	10	10	100.00
V2	multi_error	otbn_multi_err	46.000s	489.966us	1	1	100.00
V2	back_to_back	otbn_multi	2.433m	740.068us	10	10	100.00
V2	stress_all	otbn_stress_all	1.267m	204.539us	10	10	100.00
V2	lc_escalation	otbn_escalate	21.000s	39.159us	46	60	76.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	80.296us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	21.000s	369.369us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	27.783us	50	50	100.00
V2	intr_test	otbn_intr_test	15.000s	19.909us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	14.000s	198.060us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	14.000s	198.060us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	10.000s	18.320us	5	5	100.00
		otbn_csr_rw	6.000s	22.263us	20	20	100.00
		otbn_csr_aliasing	6.000s	22.798us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	92.130us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	10.000s	18.320us	5	5	100.00
		otbn_csr_rw	6.000s	22.263us	20	20	100.00
		otbn_csr_aliasing	6.000s	22.798us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	92.130us	20	20	100.00
V2		TOTAL			231	246	93.90
V2S	mem_integrity	otbn_imem_err	12.000s	39.471us	10	10	100.00
		otbn_dmem_err	15.000s	64.099us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	111.384us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	115.768us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	37.827us	5	5	100.00
		otbn_urnd_err	9.000s	15.329us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	31.945us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	133.287us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	24.000s	154.954us	0	5	0.00
		otbn_tl_intg_err	29.000s	175.455us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	45.000s	242.685us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	prim_count_check	otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	77.204us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	15.000s	64.099us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	39.471us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	29.000s	175.455us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	21.000s	39.159us	46	60	76.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	39.471us	10	10	100.00
		otbn_dmem_err	15.000s	64.099us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	80.296us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	31.945us	5	5	100.00
		otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.067m	306.955us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	39.471us	10	10	100.00
		otbn_dmem_err	15.000s	64.099us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	80.296us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	31.945us	5	5	100.00
		otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	21.000s	39.159us	46	60	76.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	39.471us	10	10	100.00
		otbn_dmem_err	15.000s	64.099us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	80.296us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	31.945us	5	5	100.00
		otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.067m	306.955us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	26.740us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	29.698us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	43.000s	227.064us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	43.000s	227.064us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	21.536us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	17.000s	138.390us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	98.422us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	98.422us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	21.000s	163.850us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.067m	306.955us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.067m	306.955us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.067m	306.955us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.433m	740.068us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.067m	306.955us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.067m	306.955us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	30.000s	83.872us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.067m	306.955us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	24.000s	154.954us	0	5	0.00
V2S		TOTAL			146	153	95.42
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	13.450m	3.212ms	7	10	70.00
V3		TOTAL			7	10	70.00
	Unmapped tests	otbn_partial_wipe	13.000s	55.049us	9	10	90.00
		TOTAL			558	585	95.38

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.71	99.53	94.29	99.63	93.19	91.84	94.87	87.06	95.80

Failure Buckets

UVM_FATAL (otbn_scoreboard.sv:540) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 5 failures:

Test otbn_escalate has 5 failures.

0.otbn_escalate.12581620080543284829300634666817445352203632682163033963708618113172596634797
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

  UVM_FATAL @  13682144 ps: (otbn_scoreboard.sv:540) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  13682144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_escalate.90443812780646764576833704324269385354335346932437789074531225858990523972249
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  UVM_FATAL @  11184771 ps: (otbn_scoreboard.sv:540) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  11184771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

6.otbn_escalate.88081999671658039938982986427224761948768810055657090986556767941122014472228
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 7053965 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   7053965 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   7053965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.otbn_escalate.73799210365787212334742580710582996501569723144751170066239782310407292308076
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 48689579 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 48689579 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  48689579 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  48689579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_zero_state_err_urnd has 1 failures.

3.otbn_zero_state_err_urnd.57358369073479771603394791932889002236371907724172125850858931095407485674603
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 53118249 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  53118249 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  53118249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

12.otbn_escalate.95730826922450213972860720742196238952190794279566368100229195392769281559262
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 72000278 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  72000278 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  72000278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

51.otbn_escalate.25779805769783583488654729559414587602188983825103826834458302196739805492415
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/51.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 60990224 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  60990224 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  60990224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,153): Assertion RvalidKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

0.otbn_sec_cm.64684195524320477827096702657966845816667287831874433948445335219809069968994
Line 309, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 27004250 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,679): (time 27004250 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,680): (time 27004250 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutKnownIfFifoKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 27004250 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.u_reqfifo.DataKnown_A has failed
  UVM_ERROR @  27004250 ps: (prim_fifo_sync.sv:153) [ASSERT FAILED] RvalidKnown_A

2.otbn_sec_cm.4242054507742731745906493050791397353065186918849910098310035063112924122518
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 21921872 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,679): (time 21921872 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,680): (time 21921872 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutKnownIfFifoKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 21921872 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.u_reqfifo.DataKnown_A has failed
  UVM_ERROR @  21921872 ps: (prim_fifo_sync.sv:153) [ASSERT FAILED] RvalidKnown_A

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

3.otbn_sec_cm.79662878320695596147034032729881420568887753074412537304262925356381448540415
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 4405301 PS) Assertion tb.dut.u_tlul_adapter_sram_imem.u_sramreqfifo.DataKnown_A has failed
  UVM_ERROR @   4405301 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   4405301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_cm.14601982018280191960587288051437184252184667706796423216772723479943978973550
Line 339, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 178138878 PS) Assertion tb.dut.u_tlul_adapter_sram_imem.u_sramreqfifo.DataKnown_A has failed
  UVM_ERROR @ 178138878 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 178138878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

9.otbn_escalate.75262943927280582941301250617973339638266410256450859638220429912157403535784
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2938781 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2938781 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2938781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

53.otbn_escalate.37479053517619627551778940546779184331172526866083373172987490136586948682234
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2849144 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2849144 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2849144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.5760276580519760696701198738028195127495812937934949788756974067890125138517
    Line 422, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 918351944 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @ 918351944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:484) [otbn_stack_addr_integ_chk_vseq] Timed out waiting for OTBN run to complete by polling status has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 1.otbn_stack_addr_integ_chk.102757068396970562191022472878978857617429663218749162551965076671529460990181
    Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 1025348440 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] Timed out waiting for OTBN run to complete by polling status
  UVM_INFO @ 1025348440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_common_*/rtl/tlul_assert.sv,315): Assertion dKnown_AKnownEnable has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

1.otbn_sec_cm.15323770156557225066541371284869345530121348430358368095145590106865957539435
Line 531, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,315): (time 154953570 PS) Assertion tb.dut.tlul_checker.dKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 154953570 PS) Assertion tb.dut.TlODValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 154953570 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 154953570 PS) Assertion tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,679): (time 154953570 PS) Assertion tb.dut.u_tlul_adapter_sram_imem.TlOutValidKnown_A has failed

Exit reason: Error: User command failed UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:96) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 3.otbn_rf_base_intg_err.103471519585476817887621968520060540495738166967473363392591061586462567395970
    Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  30440728 ps: (otbn_rf_base_intg_err_vseq.sv:96) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
  UVM_INFO @  30440728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.74187852734560723078355914764257930040948251070912613332638999523761187872344
    Line 324, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  11599276 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  11599276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 4.otbn_partial_wipe.47569366516526753400779319499363042286382515036639072526875461872245214031466
    Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 10734233 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  10734233 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  10734233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job otbn-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.66725481535745925916514245986615527701008929704345609617834324322519493036649
    Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:02a200a2-dfbd-4ca2-ab0f-ec582e0099fc
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_single has 1 failures.

36.otbn_single.24589606313333433792541150020489224381878955342803764843694668785037190140829
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5446, which encodes to -2723, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1