a8c9c17a8c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 13.000s | 107.060us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 45.000s | 489.685us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 7.000s | 26.522us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 7.000s | 31.368us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 218.208us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 10.000s | 19.625us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 9.000s | 522.466us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 7.000s | 31.368us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 10.000s | 19.625us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 48.000s | 1.248ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 20.000s | 131.064us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 41.000s | 85.384us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 41.000s | 297.230us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 1.300m | 244.320us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.150m | 430.425us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 15.000s | 50.248us | 51 | 60 | 85.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 13.000s | 277.564us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 20.000s | 234.433us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 11.000s | 20.765us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 10.000s | 24.722us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 10.000s | 50.285us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 10.000s | 50.285us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 7.000s | 26.522us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 31.368us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 10.000s | 19.625us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 9.000s | 18.168us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 7.000s | 26.522us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 31.368us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 10.000s | 19.625us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 9.000s | 18.168us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 237 | 246 | 96.34 | |||
| V2S | mem_integrity | otbn_imem_err | 15.000s | 22.771us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 60.585us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 11.000s | 108.983us | 4 | 5 | 80.00 |
| otbn_controller_ispr_rdata_err | 13.000s | 220.719us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 13.000s | 111.250us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 8.000s | 29.237us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 12.000s | 49.506us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 7.000s | 49.227us | 2 | 2 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 8.000s | 25.296us | 8 | 10 | 80.00 |
| V2S | tl_intg_err | otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 |
| otbn_tl_intg_err | 27.000s | 427.614us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 39.000s | 421.879us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 |
| V2S | prim_count_check | otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 13.000s | 107.060us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 14.000s | 60.585us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 15.000s | 22.771us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 27.000s | 427.614us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 15.000s | 50.248us | 51 | 60 | 85.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 15.000s | 22.771us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 60.585us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 13.000s | 277.564us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 12.000s | 49.506us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 45.000s | 489.685us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 15.000s | 22.771us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 60.585us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 13.000s | 277.564us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 12.000s | 49.506us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 15.000s | 50.248us | 51 | 60 | 85.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 15.000s | 22.771us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 60.585us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 13.000s | 277.564us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 12.000s | 49.506us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 45.000s | 489.685us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 10.000s | 120.446us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 9.000s | 23.392us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 31.000s | 274.410us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 31.000s | 274.410us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 11.000s | 68.883us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 14.000s | 89.238us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 12.000s | 1.013ms | 2 | 5 | 40.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 12.000s | 1.013ms | 2 | 5 | 40.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 9.000s | 75.247us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 45.000s | 489.685us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 45.000s | 489.685us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 45.000s | 489.685us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.300m | 244.320us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 45.000s | 489.685us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 45.000s | 489.685us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 26.000s | 100.113us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 45.000s | 489.685us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 11.000s | 177.216us | 0 | 5 | 0.00 |
| V2S | TOTAL | 151 | 163 | 92.64 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 15.750m | 3.938ms | 9 | 10 | 90.00 |
| V3 | TOTAL | 9 | 10 | 90.00 | |||
| TOTAL | 563 | 585 | 96.24 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 11 | 11 | 10 | 90.91 |
| V2S | 20 | 20 | 15 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.77 | 99.57 | 94.91 | 99.64 | 93.16 | 92.18 | 94.87 | 88.00 | 95.80 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 6 failures:
10.otbn_escalate.38515640271953100620830293126475719658777026797310242058098493637025082829508
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6510524 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 6510524 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 6510524 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 6510524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.otbn_escalate.3815686776928898654856951744097311784703361381789483471943785846920626311061
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6893804 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 6893804 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 6893804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 3 failures:
1.otbn_sec_cm.115645798534543790880269576392131396679408476245802982343307497388206642839728
Line 313, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 15532673 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.u_sramreqfifo.DataKnown_A has failed
UVM_ERROR @ 15532673 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 15532673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_sec_cm.47651823525702619825801242661327585995157748785962361068516527994723050516343
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 25793801 PS) Assertion tb.dut.u_tlul_adapter_sram_imem.u_sramreqfifo.DataKnown_A has failed
UVM_ERROR @ 25793801 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 25793801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:
Test otbn_alu_bignum_mod_err has 1 failures.
4.otbn_alu_bignum_mod_err.46486054823688198118584848918595108484965669011230974904718156506612732060483
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_alu_bignum_mod_err/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6162, which encodes to -3081, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_rf_bignum_intg_err has 1 failures.
6.otbn_rf_bignum_intg_err.60647471943720453423352575671735005375975508317367978660241894359917352696278
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_bignum_intg_err/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4602, which encodes to -2301, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_partial_wipe has 1 failures.
9.otbn_partial_wipe.49668453035501464846032333830229723244088012310521754617219219445818076731134
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_partial_wipe/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4382, which encodes to -2191, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:
Test otbn_stack_addr_integ_chk has 1 failures.
1.otbn_stack_addr_integ_chk.77224887383969105891192951668319286116734758472540256937566315748464560260643
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13496245 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 13496245 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 13496245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 1 failures.
17.otbn_escalate.41274267948560256719872507390509785786588374503999523464787584840828147145679
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 112548744 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 112548744 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 112548744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:484) [otbn_stack_addr_integ_chk_vseq] Timed out waiting for OTBN run to complete by polling status has 2 failures:
2.otbn_stack_addr_integ_chk.24352760623711126869199526917448027311514757279840094244275549326520372028135
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 1012505677 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] Timed out waiting for OTBN run to complete by polling status
UVM_INFO @ 1012505677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_stack_addr_integ_chk.105183297925050817859193801658350868798462760794184320135615327191948209469016
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 1016269540 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] Timed out waiting for OTBN run to complete by polling status
UVM_INFO @ 1016269540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
0.otbn_escalate.86765921287293814707642323015708611926646587037751569986650790615153973495233
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4278555 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4278555 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 4278555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_common_*/rtl/tlul_assert.sv,315): Assertion dKnown_AKnownEnable has failed has 1 failures:
0.otbn_sec_cm.15932772577055029714696923025207367747271300562329623320283391051140113798299
Line 314, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,315): (time 177215579 PS) Assertion tb.dut.tlul_checker.dKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 177215579 PS) Assertion tb.dut.TlODValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 177215579 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 177215579 PS) Assertion tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,679): (time 177215579 PS) Assertion tb.dut.u_tlul_adapter_sram_imem.TlOutValidKnown_A has failed
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
2.otbn_partial_wipe.98674094161821923559844134974404419876913562581773028425555790275178104169301
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 6182645 PS) Assertion tb.dut.NotBusyAndDone_A has failed
UVM_ERROR @ 6182645 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
UVM_INFO @ 6182645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,153): Assertion RvalidKnown_A has failed has 1 failures:
3.otbn_sec_cm.73602975221615098200107934138186926121517735952915448499441737778813213218305
Line 325, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 71717757 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,679): (time 71717757 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,680): (time 71717757 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutKnownIfFifoKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 71717757 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.u_reqfifo.DataKnown_A has failed
UVM_ERROR @ 71717757 ps: (prim_fifo_sync.sv:153) [ASSERT FAILED] RvalidKnown_A
UVM_FATAL (otbn_scoreboard.sv:540) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
4.otbn_escalate.97839031066442313352144808005073794335713432099189861600671040843490536462982
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log
UVM_FATAL @ 3439849 ps: (otbn_scoreboard.sv:540) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 3439849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:484) [otbn_single_vseq] Timed out waiting for OTBN run to complete by polling status has 1 failures:
7.otbn_stress_all_with_rand_reset.28984224837615416818536607663213875880026956822798473034219920476622544164950
Line 579, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2183772008 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete by polling status
UVM_INFO @ 2183772008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---