OTBN Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: `dd5ad5fb77`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	158.275us	1	1	100.00
V1	single_binary	otbn_single	3.333m	1.010ms	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	17.046us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	32.161us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	225.266us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	223.968us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	60.892us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	32.161us	20	20	100.00
		otbn_csr_aliasing	6.000s	223.968us	5	5	100.00
V1	mem_walk	otbn_mem_walk	49.000s	1.257ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	917.238us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	38.000s	122.205us	10	10	100.00
V2	multi_error	otbn_multi_err	48.000s	344.642us	1	1	100.00
V2	back_to_back	otbn_multi	1.267m	636.826us	10	10	100.00
V2	stress_all	otbn_stress_all	1.217m	1.025ms	10	10	100.00
V2	lc_escalation	otbn_escalate	50.000s	210.567us	39	60	65.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	40.226us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	45.162us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	23.515us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	49.802us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	97.927us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	97.927us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	17.046us	5	5	100.00
		otbn_csr_rw	7.000s	32.161us	20	20	100.00
		otbn_csr_aliasing	6.000s	223.968us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	24.076us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	17.046us	5	5	100.00
		otbn_csr_rw	7.000s	32.161us	20	20	100.00
		otbn_csr_aliasing	6.000s	223.968us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	24.076us	20	20	100.00
V2		TOTAL			224	246	91.06
V2S	mem_integrity	otbn_imem_err	11.000s	23.266us	10	10	100.00
		otbn_dmem_err	12.000s	78.810us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	16.000s	69.670us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	219.369us	5	5	100.00
		otbn_mac_bignum_acc_err	17.000s	48.041us	5	5	100.00
		otbn_urnd_err	8.000s	14.070us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	21.659us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	21.624us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	36.832us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	12.000s	38.704us	0	5	0.00
		otbn_tl_intg_err	34.000s	205.362us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	37.000s	218.651us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	prim_count_check	otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	158.275us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	78.810us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	23.266us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	34.000s	205.362us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	50.000s	210.567us	39	60	65.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	23.266us	10	10	100.00
		otbn_dmem_err	12.000s	78.810us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	40.226us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	21.659us	5	5	100.00
		otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	3.333m	1.010ms	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	23.266us	10	10	100.00
		otbn_dmem_err	12.000s	78.810us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	40.226us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	21.659us	5	5	100.00
		otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	50.000s	210.567us	39	60	65.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	23.266us	10	10	100.00
		otbn_dmem_err	12.000s	78.810us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	40.226us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	21.659us	5	5	100.00
		otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	3.333m	1.010ms	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	24.254us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	51.842us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.083m	282.006us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.083m	282.006us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	522.366us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	21.000s	979.733us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	1.011ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	1.011ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	24.000s	38.395us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	3.333m	1.010ms	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	3.333m	1.010ms	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	3.333m	1.010ms	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.267m	636.826us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	3.333m	1.010ms	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	3.333m	1.010ms	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	13.000s	26.046us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	3.333m	1.010ms	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	12.000s	38.704us	0	5	0.00
V2S		TOTAL			153	163	93.87
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	21.000m	17.667ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			550	585	94.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	20	20	15	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.78	99.58	95.04	99.66	93.40	92.02	94.87	88.00	95.80

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 10 failures:

Test otbn_escalate has 10 failures.

2.otbn_escalate.39217983683702959060876927725109513293737171329927286099989027754745707197885
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 296523329 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 296523329 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 296523329 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 296523329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.otbn_escalate.82296020237460962970555119328419405575476493830518208467607406628072385439957
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 108338442 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 108338442 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 108338442 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 108338442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 5 failures:

Test otbn_escalate has 5 failures.

3.otbn_escalate.27116283612681632500286671390238699487839064122810291792239180193018802229351
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1359936 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1359936 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1359936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.otbn_escalate.51462400550848565860263431863647690224632986101476835752898132225823136852982
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2320228 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2320228 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2320228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

1.otbn_sec_cm.9654662164465255686579495561808306547649904665012033730907607025200579553333
Line 297, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 101136607 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.u_sramreqfifo.DataKnown_A has failed
  UVM_ERROR @ 101136607 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 101136607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_cm.40883178939278284371386499932682758738855296633314115745095520622574518465828
Line 341, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 70733003 PS) Assertion tb.dut.u_tlul_adapter_sram_imem.u_sramreqfifo.DataKnown_A has failed
  UVM_ERROR @  70733003 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  70733003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_zero_state_err_urnd has 1 failures.

2.otbn_zero_state_err_urnd.16801627152419306045553687171475137619811408907064120620522543958445142439047
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 37557959 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  37557959 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  37557959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

4.otbn_escalate.106634777155557214845560296573557609068976149418718912187539886782684444027760
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 71513140 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  71513140 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  71513140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.otbn_escalate.104419085266611697203361358029827972246223142895040236719325728006576301566482
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 38979616 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  38979616 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  38979616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:540) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:

Test otbn_escalate has 3 failures.

7.otbn_escalate.23465384661800389714027952368780541455835880687175776092174629123110112004553
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  UVM_FATAL @  24758625 ps: (otbn_scoreboard.sv:540) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  24758625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.otbn_escalate.4821738042476199346166222228279377800344255058904908671903209537599364857958
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log

  UVM_FATAL @  50599864 ps: (otbn_scoreboard.sv:540) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  50599864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_base_vseq.sv:484) [otbn_stack_addr_integ_chk_vseq] Timed out waiting for OTBN run to complete by polling status has 2 failures:
- Test otbn_stack_addr_integ_chk has 2 failures.
  - 2.otbn_stack_addr_integ_chk.30836759000856061203390332605822373836525317587640782707605178391364775800404
    Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 1010838188 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] Timed out waiting for OTBN run to complete by polling status
  UVM_INFO @ 1010838188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stack_addr_integ_chk.100946612621548393645899918755873429081689358530965638181089219623232186932544
    Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 1014371485 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] Timed out waiting for OTBN run to complete by polling status
  UVM_INFO @ 1014371485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:484) [otbn_single_vseq] Timed out waiting for OTBN run to complete by polling status has 2 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.65643491930594108576735354133814053999907344763774549655193385608203021704237
    Line 322, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1030772833 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete by polling status
  UVM_INFO @ 1030772833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otbn_single has 1 failures.
  - 79.otbn_single.112702928339350575620256338478880386031418815679078967255875555330075079150141
    Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/79.otbn_single/latest/run.log
```
  UVM_FATAL @ 1009851939 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete by polling status
  UVM_INFO @ 1009851939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,153): Assertion RvalidKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.33166055554187788142171418899346093526538020341918560821812061944917319611293
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 6587804 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,679): (time 6587804 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,680): (time 6587804 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutKnownIfFifoKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 6587804 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.u_reqfifo.DataKnown_A has failed
  UVM_ERROR @   6587804 ps: (prim_fifo_sync.sv:153) [ASSERT FAILED] RvalidKnown_A

UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 3.otbn_ctrl_redun.37282684509963574875210462654867598169275806874669204072303770768685218137403
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @  45286533 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  45286533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 4.otbn_partial_wipe.32072047007223890302893375403494193151679550654480491526438286761295104611481
    Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 14198743 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  14198743 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  14198743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_common_*/rtl/tlul_assert.sv,315): Assertion dKnown_AKnownEnable has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

4.otbn_sec_cm.20695235180494465469406948189719543269526593612889948698073168627801918914888
Line 338, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,315): (time 38703782 PS) Assertion tb.dut.tlul_checker.dKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 38703782 PS) Assertion tb.dut.TlODValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 38703782 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 38703782 PS) Assertion tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,679): (time 38703782 PS) Assertion tb.dut.u_tlul_adapter_sram_imem.TlOutValidKnown_A has failed

UVM_ERROR (cip_base_vseq.sv:829) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.79200504374423829691674661128938869854425981536427460956678780410191394114256
    Line 367, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 610417904 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 610417904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 7.otbn_rf_base_intg_err.4778163076047387202543661299920744525940568105076503172215607229195936065807
    Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 522366398 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 522366398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:540) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 14.otbn_escalate.8893460443265853017326686843490710763712211740339688349279130270727779492279
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log
```
  UVM_FATAL @  20884372 ps: (otbn_scoreboard.sv:540) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  20884372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```