548a3880d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 10.000s | 36.242us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.333m | 340.359us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 5.000s | 13.965us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 5.000s | 133.590us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 10.000s | 160.439us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 22.497us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 11.000s | 120.901us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 5.000s | 133.590us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 22.497us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 50.000s | 5.211ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 20.000s | 237.669us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 44.000s | 380.840us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 49.000s | 642.114us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 2.967m | 749.700us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 2.067m | 594.049us | 9 | 10 | 90.00 |
| V2 | lc_escalation | otbn_escalate | 44.000s | 326.592us | 48 | 60 | 80.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 9.000s | 30.345us | 4 | 5 | 80.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 22.000s | 119.250us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 11.000s | 20.872us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 6.000s | 23.885us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 12.000s | 306.080us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 12.000s | 306.080us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 5.000s | 13.965us | 5 | 5 | 100.00 |
| otbn_csr_rw | 5.000s | 133.590us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 22.497us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 46.528us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 5.000s | 13.965us | 5 | 5 | 100.00 |
| otbn_csr_rw | 5.000s | 133.590us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 22.497us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 46.528us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 232 | 246 | 94.31 | |||
| V2S | mem_integrity | otbn_imem_err | 15.000s | 29.359us | 10 | 10 | 100.00 |
| otbn_dmem_err | 23.000s | 328.078us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 19.000s | 50.267us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 12.000s | 247.582us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 13.000s | 62.511us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 8.000s | 40.585us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 11.000s | 29.683us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 7.000s | 66.637us | 2 | 2 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 8.000s | 32.509us | 8 | 10 | 80.00 |
| V2S | tl_intg_err | otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 24.000s | 435.844us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 1.050m | 400.929us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 10.000s | 36.242us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 23.000s | 328.078us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 15.000s | 29.359us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 24.000s | 435.844us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 44.000s | 326.592us | 48 | 60 | 80.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 15.000s | 29.359us | 10 | 10 | 100.00 |
| otbn_dmem_err | 23.000s | 328.078us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 30.345us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 11.000s | 29.683us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.333m | 340.359us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 15.000s | 29.359us | 10 | 10 | 100.00 |
| otbn_dmem_err | 23.000s | 328.078us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 30.345us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 11.000s | 29.683us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 44.000s | 326.592us | 48 | 60 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 15.000s | 29.359us | 10 | 10 | 100.00 |
| otbn_dmem_err | 23.000s | 328.078us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 30.345us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 11.000s | 29.683us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.333m | 340.359us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 12.000s | 39.501us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 22.578us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 42.000s | 117.092us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 42.000s | 117.092us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 12.000s | 31.780us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 13.000s | 89.561us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 22.000s | 2.014ms | 3 | 5 | 60.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 22.000s | 2.014ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 10.000s | 61.379us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.333m | 340.359us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.333m | 340.359us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.333m | 340.359us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 2.967m | 749.700us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.333m | 340.359us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.333m | 340.359us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 14.000s | 46.833us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.333m | 340.359us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 21.417m | 7.806ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 158 | 163 | 96.93 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 23.950m | 23.882ms | 8 | 10 | 80.00 |
| V3 | TOTAL | 8 | 10 | 80.00 | |||
| TOTAL | 564 | 585 | 96.41 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 11 | 11 | 8 | 72.73 |
| V2S | 20 | 20 | 17 | 85.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.88 | 99.58 | 95.09 | 99.66 | 93.37 | 93.04 | 97.44 | 90.44 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:
Test otbn_zero_state_err_urnd has 1 failures.
0.otbn_zero_state_err_urnd.63224272023450699278105330998067625581262959907824734081450388218403624848905
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 25073147 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 25073147 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 25073147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 3 failures.
8.otbn_escalate.95030133519249136570163422612295785408795136329450670464155119526244588351924
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17415226 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 17415226 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 17415226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.otbn_escalate.102327295992773706558128798851133055036473787223357479063578286741309570128692
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 753090544 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 753090544 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 753090544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_scoreboard.sv:540) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:
5.otbn_escalate.3264386634955210389815158206969946323108378494736981665750089393275076713812
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log
UVM_FATAL @ 45679018 ps: (otbn_scoreboard.sv:540) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 45679018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.otbn_escalate.63037265784207699723025575757892025832821512107288723178114371649604663754441
Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log
UVM_FATAL @ 23819797 ps: (otbn_scoreboard.sv:540) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 23819797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:
6.otbn_escalate.79755772683016435680180256704754918315822892846003245709124891737803839882192
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4276219 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4276219 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 4276219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.otbn_escalate.90970512048791468915457214175146782965647503777380793512662205860319574521829
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1053258 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1053258 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1053258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 3 failures:
13.otbn_escalate.104095238449723968947406250133376767940763984498171263172916371248125779034919
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 121085841 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 121085841 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 121085841 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 121085841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.otbn_escalate.85983785618554225477740675255560259836054889447620868818845423018258544272815
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 248653245 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 248653245 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 248653245 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 248653245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 2 failures:
0.otbn_stack_addr_integ_chk.56788973262516559838207322170164997838916271268665892627247913373781531586908
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 2014204650 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x30e10018)
UVM_INFO @ 2014204650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_stack_addr_integ_chk.57473827587185097765007138593808190208529323740244758345765606854795151574409
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 2084709407 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0xe85f0018)
UVM_INFO @ 2084709407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
1.otbn_stress_all_with_rand_reset.57928961271793102705570304823143584505485820772597361205410425263550425720925
Line 556, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1274972818 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1274972818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_stress_all_with_rand_reset.19287799263078068407331271681157276144309473650533022228712103348526730654913
Line 597, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3067811479 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 3067811479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:
4.otbn_partial_wipe.44967797349253337029939765257042004982952734569951140557882734555340673310401
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 7117983 PS) Assertion tb.dut.NotBusyAndDone_A has failed
UVM_ERROR @ 7117983 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
UVM_INFO @ 7117983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.otbn_partial_wipe.20480764505349167249246078720993945086773762221121028032350506769824324289544
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 39640259 PS) Assertion tb.dut.NotBusyAndDone_A has failed
UVM_ERROR @ 39640259 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
UVM_INFO @ 39640259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:
1.otbn_stress_all.57531141214599265912927228043850251483917585162790871798709261746194970011541
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6186, which encodes to -3093, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
9.otbn_rf_base_intg_err.15918490156871216140589465109888329287057866003548426239081352543938578430820
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 38022289 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
UVM_INFO @ 38022289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---