OTBN Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	74.835us	1	1	100.00
V1	single_binary	otbn_single	2.500m	613.555us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	19.737us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	18.883us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	93.813us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	12.128us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	63.933us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	18.883us	20	20	100.00
		otbn_csr_aliasing	5.000s	12.128us	5	5	100.00
V1	mem_walk	otbn_mem_walk	56.000s	3.634ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	1.410ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	49.000s	208.615us	10	10	100.00
V2	multi_error	otbn_multi_err	50.000s	469.009us	1	1	100.00
V2	back_to_back	otbn_multi	1.650m	792.286us	10	10	100.00
V2	stress_all	otbn_stress_all	1.850m	1.097ms	10	10	100.00
V2	lc_escalation	otbn_escalate	21.000s	56.558us	56	60	93.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	21.624us	2	5	40.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	78.063us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	24.176us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	22.648us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	142.009us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	142.009us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	19.737us	5	5	100.00
		otbn_csr_rw	6.000s	18.883us	20	20	100.00
		otbn_csr_aliasing	5.000s	12.128us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	29.061us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	19.737us	5	5	100.00
		otbn_csr_rw	6.000s	18.883us	20	20	100.00
		otbn_csr_aliasing	5.000s	12.128us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	29.061us	20	20	100.00
V2		TOTAL			239	246	97.15
V2S	mem_integrity	otbn_imem_err	12.000s	31.755us	10	10	100.00
		otbn_dmem_err	18.000s	73.589us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	25.000s	82.729us	5	5	100.00
		otbn_controller_ispr_rdata_err	10.000s	217.032us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	32.528us	5	5	100.00
		otbn_urnd_err	7.000s	14.070us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	17.150us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	26.175us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	19.982us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	16.083m	5.397ms	5	5	100.00
		otbn_tl_intg_err	30.000s	175.911us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	38.000s	198.246us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	74.835us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	18.000s	73.589us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	31.755us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	30.000s	175.911us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	21.000s	56.558us	56	60	93.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	31.755us	10	10	100.00
		otbn_dmem_err	18.000s	73.589us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	21.624us	2	5	40.00
		otbn_illegal_mem_acc	8.000s	17.150us	5	5	100.00
		otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.500m	613.555us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	31.755us	10	10	100.00
		otbn_dmem_err	18.000s	73.589us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	21.624us	2	5	40.00
		otbn_illegal_mem_acc	8.000s	17.150us	5	5	100.00
		otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	21.000s	56.558us	56	60	93.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	31.755us	10	10	100.00
		otbn_dmem_err	18.000s	73.589us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	21.624us	2	5	40.00
		otbn_illegal_mem_acc	8.000s	17.150us	5	5	100.00
		otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.500m	613.555us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	21.289us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	22.623us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	47.000s	939.296us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	47.000s	939.296us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	19.000s	261.076us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	217.109us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	43.000s	2.004ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	43.000s	2.004ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	17.000s	56.241us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.500m	613.555us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.500m	613.555us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.500m	613.555us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.650m	792.286us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.500m	613.555us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.500m	613.555us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	14.000s	110.444us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.500m	613.555us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	16.083m	5.397ms	5	5	100.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.400m	10.117ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			573	585	97.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.90	99.60	95.35	99.69	93.40	92.78	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_zero_state_err_urnd has 3 failures.

0.otbn_zero_state_err_urnd.101532989639321805623486689985962893582914903556530990513668446636147718326879
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22616460 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  22616460 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  22616460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_zero_state_err_urnd.32456082319740446463942717298467839247327151061647392846276359442683251678039
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 9973445 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   9973445 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   9973445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

29.otbn_escalate.107844443350247096441935057205788996320534937817890507726859798519834151290018
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 8086082 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   8086082 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   8086082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.otbn_escalate.115471558469606514471596802808585298358473621637107141644080630617428960576300
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/33.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 1107544 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   1107544 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   1107544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 2 failures:
- Test otbn_stack_addr_integ_chk has 2 failures.
  - 1.otbn_stack_addr_integ_chk.62335900556141716050345479888124930930299823782194135866106802741367276387961
    Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 2015663765 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x751f0018)
  UVM_INFO @ 2015663765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.otbn_stack_addr_integ_chk.25843126293858981103702986317342607007450450541158517557028019979069570944000
    Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 2004292062 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x8b860018)
  UVM_INFO @ 2004292062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

0.otbn_stress_all_with_rand_reset.71315273908105290168810550066530652687228828971077027881129827461366101226529
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4882, which encodes to -2441, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,969): Assertion OnlyWriteLoadDataBignumWhenDMemValid_A has failed has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 0.otbn_ctrl_redun.31794231775910051141032047793255336071486385284995640045197585530800497377679
    Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,969): (time 24594815 PS) Assertion tb.dut.u_otbn_core.OnlyWriteLoadDataBignumWhenDMemValid_A has failed
  UVM_ERROR @  24594815 ps: (otbn_core.sv:969) [ASSERT FAILED] OnlyWriteLoadDataBignumWhenDMemValid_A
  UVM_INFO @  24594815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 3.otbn_partial_wipe.92767637949737761280800210233931047214314016400073408028245519609265170722127
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 20419485 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  20419485 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  20419485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 28.otbn_escalate.59166597177821149680884691272714576817639436022792385744059365862268948540650
    Line 305, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/28.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 21818613 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  21818613 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  21818613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```