OTBN Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: `8fdb25c8d9`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	158.565us	1	1	100.00
V1	single_binary	otbn_single	57.000s	242.812us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	51.939us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	16.377us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	515.165us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	37.788us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	28.341us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	16.377us	20	20	100.00
		otbn_csr_aliasing	5.000s	37.788us	5	5	100.00
V1	mem_walk	otbn_mem_walk	43.000s	752.153us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	21.000s	1.566ms	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	51.000s	97.935us	10	10	100.00
V2	multi_error	otbn_multi_err	1.000m	564.172us	1	1	100.00
V2	back_to_back	otbn_multi	3.200m	756.739us	9	10	90.00
V2	stress_all	otbn_stress_all	1.433m	1.513ms	10	10	100.00
V2	lc_escalation	otbn_escalate	27.000s	128.529us	47	60	78.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	17.681us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	72.506us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	17.649us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	19.873us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	38.757us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	38.757us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	51.939us	5	5	100.00
		otbn_csr_rw	6.000s	16.377us	20	20	100.00
		otbn_csr_aliasing	5.000s	37.788us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	43.720us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	51.939us	5	5	100.00
		otbn_csr_rw	6.000s	16.377us	20	20	100.00
		otbn_csr_aliasing	5.000s	37.788us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	43.720us	20	20	100.00
V2		TOTAL			232	246	94.31
V2S	mem_integrity	otbn_imem_err	10.000s	48.730us	10	10	100.00
		otbn_dmem_err	14.000s	45.177us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	58.439us	5	5	100.00
		otbn_controller_ispr_rdata_err	24.000s	92.274us	5	5	100.00
		otbn_mac_bignum_acc_err	23.000s	465.028us	5	5	100.00
		otbn_urnd_err	7.000s	17.717us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	29.327us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	88.406us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	36.573us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	7.667m	3.956ms	5	5	100.00
		otbn_tl_intg_err	48.000s	365.121us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	45.000s	238.574us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	158.565us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	14.000s	45.177us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	48.730us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	48.000s	365.121us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	27.000s	128.529us	47	60	78.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	48.730us	10	10	100.00
		otbn_dmem_err	14.000s	45.177us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	17.681us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	29.327us	5	5	100.00
		otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	57.000s	242.812us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	48.730us	10	10	100.00
		otbn_dmem_err	14.000s	45.177us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	17.681us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	29.327us	5	5	100.00
		otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	27.000s	128.529us	47	60	78.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	48.730us	10	10	100.00
		otbn_dmem_err	14.000s	45.177us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	17.681us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	29.327us	5	5	100.00
		otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	57.000s	242.812us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	16.000s	83.109us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	107.246us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	52.000s	785.311us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	52.000s	785.311us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	22.871us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	146.574us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	30.332us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	30.332us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	20.000s	62.031us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	57.000s	242.812us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	57.000s	242.812us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	57.000s	242.812us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.200m	756.739us	9	10	90.00
V2S	sec_cm_ctrl_flow_count	otbn_single	57.000s	242.812us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	57.000s	242.812us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	19.000s	431.770us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	57.000s	242.812us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.667m	3.956ms	5	5	100.00
V2S		TOTAL			161	163	98.77
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	15.267m	10.075ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			567	585	96.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.90	99.62	95.57	99.70	93.49	92.57	97.44	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 7 failures:

Test otbn_escalate has 7 failures.

25.otbn_escalate.85845406165412510308282213993461991710979495246037710301948628970160966691173
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 5897159 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   5897159 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   5897159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.otbn_escalate.104177869811901118280184241619653154291166401842464553726915081453320045147413
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/34.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 42325025 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42325025 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  42325025 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  42325025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test otbn_multi has 1 failures.

8.otbn_multi.40073444879722546111304972675177954110103517200593698678762947477389101708193
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_multi/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5082, which encodes to -2541, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_rf_base_intg_err has 1 failures.

9.otbn_rf_base_intg_err.4540885005808416243746299604302798709544036008369778629516945506258929830919
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_rf_base_intg_err/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4842, which encodes to -2421, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_single has 1 failures.

95.otbn_single.17769249099543953494337295773062706079692685807938820757129698918843601428242
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/95.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4754, which encodes to -2377, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

15.otbn_escalate.84400965682900588512034054892946236139863825680188357803161947238598446723574
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 128528578 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 128528578 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 128528578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.otbn_escalate.29042667591867937203253415493375125963272341511618907444799317713853962222075
Line 295, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 55955748 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  55955748 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  55955748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

35.otbn_escalate.4870979634960435184234106879565454318168387787236704916678480176320313588369
Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/35.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 10607217 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  10607217 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  10607217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.otbn_escalate.82573870016362113340392568712539960717155809140297801620838250178750045193494
Line 308, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/40.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 52931883 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  52931883 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  52931883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.45770684690698855340543987859984750072376168442227690639390018325387834578387
    Line 544, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4149952604 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4149952604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 5.otbn_partial_wipe.51649466467502222454321086807952097174217619076760393616682499523185462101734
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 25077166 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  25077166 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  25077166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```