OTBN Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	15.000s	47.608us	1	1	100.00
V1	single_binary	otbn_single	58.000s	257.866us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	33.084us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	24.311us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	96.775us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	16.004us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	35.328us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	24.311us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.004us	5	5	100.00
V1	mem_walk	otbn_mem_walk	59.000s	3.574ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	1.701ms	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	46.000s	1.237ms	10	10	100.00
V2	multi_error	otbn_multi_err	53.000s	981.421us	1	1	100.00
V2	back_to_back	otbn_multi	1.717m	1.299ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.517m	313.495us	10	10	100.00
V2	lc_escalation	otbn_escalate	2.950m	755.472us	50	60	83.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	59.771us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	89.166us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	171.758us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	16.510us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	95.699us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	95.699us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	33.084us	5	5	100.00
		otbn_csr_rw	7.000s	24.311us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.004us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	129.824us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	33.084us	5	5	100.00
		otbn_csr_rw	7.000s	24.311us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.004us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	129.824us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	14.000s	35.913us	10	10	100.00
		otbn_dmem_err	21.000s	74.821us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	17.000s	37.577us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	65.182us	5	5	100.00
		otbn_mac_bignum_acc_err	22.000s	249.497us	5	5	100.00
		otbn_urnd_err	7.000s	14.181us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	40.984us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	50.750us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	60.120us	7	10	70.00
V2S	tl_intg_err	otbn_sec_cm	7.400m	1.835ms	5	5	100.00
		otbn_tl_intg_err	30.000s	182.197us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	44.000s	254.799us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	15.000s	47.608us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	21.000s	74.821us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	35.913us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	30.000s	182.197us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	2.950m	755.472us	50	60	83.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	35.913us	10	10	100.00
		otbn_dmem_err	21.000s	74.821us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	59.771us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	40.984us	5	5	100.00
		otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	58.000s	257.866us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	35.913us	10	10	100.00
		otbn_dmem_err	21.000s	74.821us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	59.771us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	40.984us	5	5	100.00
		otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	2.950m	755.472us	50	60	83.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	35.913us	10	10	100.00
		otbn_dmem_err	21.000s	74.821us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	59.771us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	40.984us	5	5	100.00
		otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	58.000s	257.866us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	42.797us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	26.056us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.217m	557.395us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.217m	557.395us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	48.226us	8	10	80.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	225.309us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	19.000s	2.008ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	19.000s	2.008ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	26.000s	73.293us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	58.000s	257.866us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	58.000s	257.866us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	58.000s	257.866us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.717m	1.299ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	58.000s	257.866us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	58.000s	257.866us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	20.000s	199.821us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	58.000s	257.866us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.400m	1.835ms	5	5	100.00
V2S		TOTAL			156	163	95.71
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.233m	7.202ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			564	585	96.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.91	99.62	95.62	99.70	93.52	92.67	97.44	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 7 failures:

Test otbn_escalate has 7 failures.

1.otbn_escalate.58774914651977046688696191896718060450310850364042113676062144422216733505921
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3104943 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3104943 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3104943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.otbn_escalate.80688346825261705045197765940319605799347734129666298368665795390323270665032
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 7337374 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   7337374 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   7337374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

1.otbn_stack_addr_integ_chk.75980179083961294621496768953119231276233358214536840298136886419170894864792
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 9496982 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   9496982 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   9496982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

7.otbn_escalate.74781803111812124051063478580026882503674041115894603965471806833161413346233
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17436987 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  17436987 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  17436987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:

Test otbn_partial_wipe has 2 failures.

3.otbn_partial_wipe.7537327745127753403213767196298249057173674331390016299826558623104041156307
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 6690105 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   6690105 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   6690105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_partial_wipe.55473158616823017073319016734777720102286376281183415662667031570149722328109
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 10671514 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  10671514 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  10671514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

8.otbn_stress_all_with_rand_reset.98838220580249678851522040823708449421225982304058504173810247997755717784002
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4234, which encodes to -2117, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_single has 1 failures.

94.otbn_single.690746198833878248978385996909228834212652714955000337915022259350418045615
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/94.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5638, which encodes to -2819, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

21.otbn_escalate.78730914341044732195694418192554785675151828582083174588966419931042415742640
Line 303, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3115920 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3115920 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3115920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.otbn_escalate.11957979276809045966939784777495479745662476898846394438218538163450572915129
Line 303, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/31.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 6515053 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   6515053 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   6515053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.80409325408242377619284026534991934815455845811659293489060975061167628804932
    Line 463, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 472272809 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 472272809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 3.otbn_stack_addr_integ_chk.6173215671269521856211471086596530252218046020075580290489422127710208550797
    Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 2007918262 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0xa43f0018)
  UVM_INFO @ 2007918262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 4.otbn_rf_base_intg_err.7485915623981299730614476508244640019300606216946430454410333183876244305144
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  27616558 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  27616558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:829) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.43817648788487213543332271827838741888689233037240657812417202702026817168798
    Line 420, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 787143022 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 787143022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:198) [scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register. has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 5.otbn_partial_wipe.12114989450754298978448316176216374949727318457692619847388307144521451034443
    Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_partial_wipe/latest/run.log
```
  UVM_FATAL @  10393023 ps: (otbn_scoreboard.sv:198) [uvm_test_top.env.scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register.
  UVM_INFO @  10393023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 6.otbn_rf_base_intg_err.45328231169485958661206132975521869831976872060076033064685937614177707031613
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  33986671 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
  UVM_INFO @  33986671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```