OTBN Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	53.485us	1	1	100.00
V1	single_binary	otbn_single	1.017m	560.568us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	71.914us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	21.493us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	94.391us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	16.545us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	52.253us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	21.493us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.545us	5	5	100.00
V1	mem_walk	otbn_mem_walk	56.000s	7.093ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	1.540ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.183m	327.452us	10	10	100.00
V2	multi_error	otbn_multi_err	1.117m	149.718us	1	1	100.00
V2	back_to_back	otbn_multi	1.283m	233.001us	10	10	100.00
V2	stress_all	otbn_stress_all	2.750m	2.620ms	10	10	100.00
V2	lc_escalation	otbn_escalate	1.367m	346.313us	50	60	83.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	36.118us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	22.000s	235.016us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	17.540us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	32.093us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	244.864us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	244.864us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	71.914us	5	5	100.00
		otbn_csr_rw	7.000s	21.493us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.545us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	24.127us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	71.914us	5	5	100.00
		otbn_csr_rw	7.000s	21.493us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.545us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	24.127us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	11.000s	31.816us	10	10	100.00
		otbn_dmem_err	12.000s	24.905us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	29.442us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	65.995us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	268.457us	5	5	100.00
		otbn_urnd_err	13.000s	63.317us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	10.099us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	75.670us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	111.141us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	12.533m	4.035ms	5	5	100.00
		otbn_tl_intg_err	35.000s	224.142us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	38.000s	236.484us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	53.485us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	24.905us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	31.816us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	35.000s	224.142us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.367m	346.313us	50	60	83.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	31.816us	10	10	100.00
		otbn_dmem_err	12.000s	24.905us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	36.118us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	10.099us	5	5	100.00
		otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.017m	560.568us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	31.816us	10	10	100.00
		otbn_dmem_err	12.000s	24.905us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	36.118us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	10.099us	5	5	100.00
		otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.367m	346.313us	50	60	83.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	31.816us	10	10	100.00
		otbn_dmem_err	12.000s	24.905us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	36.118us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	10.099us	5	5	100.00
		otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.017m	560.568us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	29.980us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	84.894us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	41.000s	128.352us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	41.000s	128.352us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	71.323us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	84.813us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	25.000s	86.120us	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	25.000s	86.120us	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	20.000s	37.899us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.017m	560.568us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.017m	560.568us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.017m	560.568us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.283m	233.001us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.017m	560.568us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.017m	560.568us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	17.000s	46.446us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.017m	560.568us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	12.533m	4.035ms	5	5	100.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	9.000m	27.927ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			568	585	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.89	99.60	95.31	99.69	93.37	92.79	97.44	91.14	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

8.otbn_escalate.44699689473309255061198928448415451030271292727760338749412064284150627954104
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 21481997 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21481997 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  21481997 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  21481997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.otbn_escalate.9481855847250103840693614119572306376803861617651562201538531863304580709118
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 1378159 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   1378159 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   1378159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_ctrl_redun has 1 failures.

6.otbn_ctrl_redun.84739598551223358038974535770216599256436892033262629959930826901494692018222
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 50259616 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  50259616 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  50259616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

39.otbn_escalate.111854103002654170689794935741697117353232362472427196191275915717359767496575
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 152247689 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 152247689 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 152247689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.otbn_escalate.96190078931755224393001706068867506824968730838577953755314641811324651726044
Line 295, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/42.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21716030 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  21716030 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  21716030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

13.otbn_escalate.62021017490909275066577627780082648504988503305953701687488349661357085222699
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 12394754 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  12394754 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  12394754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.otbn_escalate.22799484417126289108898560333141645522068273145100784745993730740620893510103
Line 305, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/31.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 27107335 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  27107335 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  27107335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.54119609034268523327664182818983541264727999551998256176129992616139956846668
    Line 935, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 27927293185 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 27927293185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.otbn_stress_all_with_rand_reset.65542216334720604687977325022603134800428655174892487489016585076626452740232
    Line 630, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6737629248 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 6737629248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 0.otbn_stack_addr_integ_chk.72471559444441282521348021745773544358190555114031131888432770544107728290145
    Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 2047389074 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x58130018)
  UVM_INFO @ 2047389074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

3.otbn_stack_addr_integ_chk.44774956116057588543739364468780885032111762706507897808864101781003205938326
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4658, which encodes to -2329, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 6.otbn_rf_base_intg_err.12520941529554318964793011805482410331255807570505881705347223960137261931684
    Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  24918112 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
  UVM_INFO @  24918112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.err_bits (addr=*) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.37703938077246548347414528285442829872924510321533816247416740701693005948381
    Line 510, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3377152761 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.err_bits (addr=0xf831001c)
  UVM_INFO @ 3377152761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```