OTBN Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	44.395us	1	1	100.00
V1	single_binary	otbn_single	1.717m	860.415us	98	100	98.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	26.534us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	15.203us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	518.148us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	25.339us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	77.646us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	15.203us	20	20	100.00
		otbn_csr_aliasing	6.000s	25.339us	5	5	100.00
V1	mem_walk	otbn_mem_walk	55.000s	3.561ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	1.590ms	5	5	100.00
V1		TOTAL			164	166	98.80
V2	reset_recovery	otbn_reset	42.000s	162.694us	10	10	100.00
V2	multi_error	otbn_multi_err	56.000s	1.230ms	1	1	100.00
V2	back_to_back	otbn_multi	23.967m	4.016ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.150m	603.975us	10	10	100.00
V2	lc_escalation	otbn_escalate	29.000s	1.066ms	51	60	85.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	20.448us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	16.000s	53.443us	10	10	100.00
V2	alert_test	otbn_alert_test	21.000s	14.296us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	30.196us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	156.160us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	156.160us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	26.534us	5	5	100.00
		otbn_csr_rw	6.000s	15.203us	20	20	100.00
		otbn_csr_aliasing	6.000s	25.339us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	46.425us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	26.534us	5	5	100.00
		otbn_csr_rw	6.000s	15.203us	20	20	100.00
		otbn_csr_aliasing	6.000s	25.339us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	46.425us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	15.000s	35.780us	10	10	100.00
		otbn_dmem_err	17.000s	39.592us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	20.000s	403.741us	5	5	100.00
		otbn_controller_ispr_rdata_err	16.000s	258.361us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	36.222us	5	5	100.00
		otbn_urnd_err	6.000s	16.131us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	23.736us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	40.180us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	34.623us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	6.733m	1.916ms	5	5	100.00
		otbn_tl_intg_err	29.000s	203.154us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	47.000s	250.678us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	44.395us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	17.000s	39.592us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	35.780us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	29.000s	203.154us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	29.000s	1.066ms	51	60	85.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	35.780us	10	10	100.00
		otbn_dmem_err	17.000s	39.592us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	20.448us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	23.736us	5	5	100.00
		otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.717m	860.415us	98	100	98.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	35.780us	10	10	100.00
		otbn_dmem_err	17.000s	39.592us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	20.448us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	23.736us	5	5	100.00
		otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	29.000s	1.066ms	51	60	85.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	35.780us	10	10	100.00
		otbn_dmem_err	17.000s	39.592us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	20.448us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	23.736us	5	5	100.00
		otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.717m	860.415us	98	100	98.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	19.000s	93.890us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	36.746us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.317m	1.793ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.317m	1.793ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	18.000s	67.598us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	2.800m	1.883ms	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	35.233m	200.000ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	35.233m	200.000ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	148.114us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.717m	860.415us	98	100	98.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.717m	860.415us	98	100	98.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.717m	860.415us	98	100	98.00
V2S	sec_cm_write_mem_integrity	otbn_multi	23.967m	4.016ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.717m	860.415us	98	100	98.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.717m	860.415us	98	100	98.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	1.900m	500.288us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.717m	860.415us	98	100	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.733m	1.916ms	5	5	100.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.200m	13.639ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			570	585	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	20	20	18	90.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.91	99.62	95.57	99.70	93.52	92.78	97.44	91.49	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_zero_state_err_urnd has 1 failures.

2.otbn_zero_state_err_urnd.48354504436583961721589242291996766907050710197557565374780941979298164631712
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 71445980 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  71445980 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  71445980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 3 failures.

20.otbn_escalate.91069568746325041730213002360406251212278744019462093762960251122387435202632
Line 294, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 62758959 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  62758959 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  62758959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.otbn_escalate.76515771708083284644629709172633379858145213324385166062697743246522369301797
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/37.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 44904185 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  44904185 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  44904185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

16.otbn_escalate.6348541887816303305647687839651554310065702370823818786791933201446580619017
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 4001608 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   4001608 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   4001608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.otbn_escalate.14029252700948537313605695047112355866934016146043578826188091318275357481322
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/43.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 4103401 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   4103401 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   4103401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 2.otbn_stack_addr_integ_chk.64670570684570597722280123926349700312436249882925364156904683167978222619903
    Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 2008934939 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x19cc0018)
  UVM_INFO @ 2008934939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:198) [scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register. has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 2.otbn_partial_wipe.20956527867893016457059084705024496438150097632486195200910520830439042821612
    Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log
```
  UVM_FATAL @  11415546 ps: (otbn_scoreboard.sv:198) [uvm_test_top.env.scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register.
  UVM_INFO @  11415546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 3.otbn_stack_addr_integ_chk.24375471564177420767772587739139442170327540338254715428342911586701089953005
    Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_single has 1 failures.

31.otbn_single.114452480598948096792835723088425220150552514389779133529837667307894917410679
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/31.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5222, which encodes to -2611, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 36.otbn_escalate.27652814331958822911239329112421861194023527185950109879979032877587179889206
    Line 308, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 76401665 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  76401665 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  76401665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 52.otbn_escalate.76800649822279340773070681671622784621345169934462648071993034731081843716692
    Line 303, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/52.otbn_escalate/latest/run.log
```
  UVM_FATAL @   9605663 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   9605663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_single has 1 failures.
  - 96.otbn_single.1071732385999053928714344992887012440637663011080118742649404898126247754368
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/96.otbn_single/latest/run.log
```
  UVM_FATAL @  23610344 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  23610344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```