OTBN Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	77.553us	1	1	100.00
V1	single_binary	otbn_single	2.467m	741.759us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	15.819us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	18.393us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	526.435us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	11.000s	25.428us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	19.000s	163.849us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	18.393us	20	20	100.00
		otbn_csr_aliasing	11.000s	25.428us	5	5	100.00
V1	mem_walk	otbn_mem_walk	53.000s	2.426ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	379.986us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	55.000s	262.366us	9	10	90.00
V2	multi_error	otbn_multi_err	1.017m	514.247us	1	1	100.00
V2	back_to_back	otbn_multi	1.567m	406.118us	8	10	80.00
V2	stress_all	otbn_stress_all	1.417m	245.305us	10	10	100.00
V2	lc_escalation	otbn_escalate	22.000s	91.335us	51	60	85.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	18.301us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	71.746us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	36.780us	50	50	100.00
V2	intr_test	otbn_intr_test	19.000s	12.140us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	17.000s	141.860us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	17.000s	141.860us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	15.819us	5	5	100.00
		otbn_csr_rw	10.000s	18.393us	20	20	100.00
		otbn_csr_aliasing	11.000s	25.428us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	33.767us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	15.819us	5	5	100.00
		otbn_csr_rw	10.000s	18.393us	20	20	100.00
		otbn_csr_aliasing	11.000s	25.428us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	33.767us	20	20	100.00
V2		TOTAL			234	246	95.12
V2S	mem_integrity	otbn_imem_err	14.000s	35.572us	10	10	100.00
		otbn_dmem_err	14.000s	174.046us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	27.183us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	58.901us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	22.805us	5	5	100.00
		otbn_urnd_err	7.000s	15.908us	1	2	50.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	56.256us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	12.000s	47.445us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	63.065us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	6.400m	3.639ms	5	5	100.00
		otbn_tl_intg_err	32.000s	1.661ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	32.000s	174.321us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	77.553us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	14.000s	174.046us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	35.572us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	32.000s	1.661ms	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	22.000s	91.335us	51	60	85.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	35.572us	10	10	100.00
		otbn_dmem_err	14.000s	174.046us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	18.301us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	56.256us	5	5	100.00
		otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.467m	741.759us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	35.572us	10	10	100.00
		otbn_dmem_err	14.000s	174.046us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	18.301us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	56.256us	5	5	100.00
		otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	22.000s	91.335us	51	60	85.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	35.572us	10	10	100.00
		otbn_dmem_err	14.000s	174.046us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	18.301us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	56.256us	5	5	100.00
		otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.467m	741.759us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	13.000s	41.054us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	27.394us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	2.033m	549.890us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	2.033m	549.890us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	24.565us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	18.000s	58.690us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	10.883m	200.000ms	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	10.883m	200.000ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	21.356us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.467m	741.759us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.467m	741.759us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.467m	741.759us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.567m	406.118us	8	10	80.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.467m	741.759us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.467m	741.759us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	37.088us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.467m	741.759us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.400m	3.639ms	5	5	100.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	9.000m	1.735ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			568	585	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	8	72.73
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.90	99.60	95.40	99.69	93.52	92.87	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 4 failures:

Test otbn_reset has 1 failures.

1.otbn_reset.114849688694414267662187256332400191150604039299203962293969448667855158479055
Line 309, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 111778752 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @ 111778752 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 111778752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 3 failures.

1.otbn_escalate.103470874605958713755704439649404626114796870862714515635626278541921198910025
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 81555376 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 81555376 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  81555376 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  81555376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.otbn_escalate.38359106073510980588685012172457458258704193644052325996338700510084302222288
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 19717665 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19717665 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19717665 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  19717665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_escalate has 3 failures.

3.otbn_escalate.103436707005431999690479220271252500796178098214765211228948583956243738256805
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42675965 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  42675965 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  42675965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.otbn_escalate.27202809898771848968679003576916199699619240580891423185528736205685420076975
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 122599404 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 122599404 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 122599404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otbn_ctrl_redun has 1 failures.

3.otbn_ctrl_redun.106851928195264029856617437430684349385003571442142192873074438841458461487764
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17723079 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  17723079 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  17723079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test otbn_urnd_err has 1 failures.

0.otbn_urnd_err.29391056451587051420235545642205549997551913546994153065358186210303195041151
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_urnd_err/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5046, which encodes to -2523, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_multi has 2 failures.

3.otbn_multi.80366047066948731656744000260834969396729402826893404448999577923806307144583
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_multi/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6434, which encodes to -3217, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

5.otbn_multi.106625792411894119669882449637798099326368054438365241099718386797488030277943
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_multi/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5862, which encodes to -2931, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

9.otbn_escalate.95090171312919256135655417410152760074611791065574701972084394402955501705181
Line 307, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 30137390 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  30137390 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  30137390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.otbn_escalate.49093370864917690846510883667530120468210299473073313289025320859720456193810
Line 308, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 208261714 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @ 208261714 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @ 208261714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.111642777513773936439870703302687337239800418857449366868769686339055897356508
    Line 373, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 574140331 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 574140331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 3.otbn_stack_addr_integ_chk.75445290928612839289702133933352371526239037590481422883686833481506350088946
    Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.107626535036596766460373105983271754468561666963473832549763604580912526842096
    Line 701, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3882849033 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3882849033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```