OTBN Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	44.288us	1	1	100.00
V1	single_binary	otbn_single	1.117m	345.768us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	43.024us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	22.432us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	511.695us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	19.543us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	41.496us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	22.432us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.543us	5	5	100.00
V1	mem_walk	otbn_mem_walk	54.000s	3.630ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	1.749ms	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	44.000s	478.486us	10	10	100.00
V2	multi_error	otbn_multi_err	1.067m	1.143ms	1	1	100.00
V2	back_to_back	otbn_multi	3.567m	1.536ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.667m	473.919us	10	10	100.00
V2	lc_escalation	otbn_escalate	49.000s	692.786us	49	60	81.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	38.700us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	61.627us	9	10	90.00
V2	alert_test	otbn_alert_test	7.000s	13.403us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	39.685us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	44.463us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	44.463us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	43.024us	5	5	100.00
		otbn_csr_rw	6.000s	22.432us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.543us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	29.739us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	43.024us	5	5	100.00
		otbn_csr_rw	6.000s	22.432us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.543us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	29.739us	20	20	100.00
V2		TOTAL			234	246	95.12
V2S	mem_integrity	otbn_imem_err	13.000s	43.013us	10	10	100.00
		otbn_dmem_err	27.000s	122.503us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	40.307us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	58.676us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	102.769us	5	5	100.00
		otbn_urnd_err	7.000s	48.589us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	24.897us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	62.010us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	60.502us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	9.267m	3.059ms	5	5	100.00
		otbn_tl_intg_err	45.000s	388.398us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	41.000s	246.064us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	44.288us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	27.000s	122.503us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	43.013us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	45.000s	388.398us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	49.000s	692.786us	49	60	81.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	43.013us	10	10	100.00
		otbn_dmem_err	27.000s	122.503us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	38.700us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.897us	5	5	100.00
		otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.117m	345.768us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	43.013us	10	10	100.00
		otbn_dmem_err	27.000s	122.503us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	38.700us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.897us	5	5	100.00
		otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	49.000s	692.786us	49	60	81.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	43.013us	10	10	100.00
		otbn_dmem_err	27.000s	122.503us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	38.700us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.897us	5	5	100.00
		otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.117m	345.768us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	20.767us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	54.635us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	50.000s	319.928us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	50.000s	319.928us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	63.256us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	250.502us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	27.000s	97.722us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	27.000s	97.722us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	29.682us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.117m	345.768us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.117m	345.768us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.117m	345.768us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.567m	1.536ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.117m	345.768us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.117m	345.768us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	21.494us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.117m	345.768us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	9.267m	3.059ms	5	5	100.00
V2S		TOTAL			163	163	100.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	21.100m	29.774ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			570	585	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	20	20	20	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.60	95.40	99.69	93.52	92.37	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 6 failures:

Test otbn_escalate has 6 failures.

5.otbn_escalate.102224187418621250502582637431666648468159982864736995235648875605423165278609
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 205992124 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 205992124 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 205992124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.otbn_escalate.54310814384033005877600870189259528958669281235142986789848281421441686710421
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 35706255 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  35706255 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  35706255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

1.otbn_escalate.9447098967321839898458488094245690158861923362500745017507154062238495749622
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 2231802 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   2231802 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   2231802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

57.otbn_escalate.4554417609457580766779664498157302096802450929768049145389594477547097149615
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/57.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 150834811 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 150834811 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 150834811 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 150834811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test otbn_sw_errs_fatal_chk has 1 failures.

0.otbn_sw_errs_fatal_chk.60589176013866603967087276522409526503074480181347169787175700316835584804914
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4966, which encodes to -2483, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_single has 1 failures.

34.otbn_single.57539137058810105867334753489920505927820400299121987938684392209809633675480
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/34.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4290, which encodes to -2145, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

16.otbn_escalate.16062354208236925994501826559307638396242118285230566802535409408690233765195
Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 9218841 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   9218841 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   9218841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

51.otbn_escalate.48496237384824216735554776519876399406220104467781916047302651722312105459360
Line 307, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/51.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 52179628 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  52179628 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  52179628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.32770852164277431922848161376801864079500869740273171620545445578141448562026
    Line 462, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 922976692 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 922976692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:829) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.21852612267000694027519046593321152613114592598135797655676044959632923156875
    Line 905, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2176251988 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2176251988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```