OTBN Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	36.782us	1	1	100.00
V1	single_binary	otbn_single	1.983m	477.159us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	35.867us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	18.844us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	233.181us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	14.018us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	173.599us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	18.844us	20	20	100.00
		otbn_csr_aliasing	6.000s	14.018us	5	5	100.00
V1	mem_walk	otbn_mem_walk	53.000s	1.900ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	1.414ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	43.000s	109.548us	10	10	100.00
V2	multi_error	otbn_multi_err	55.000s	284.178us	1	1	100.00
V2	back_to_back	otbn_multi	5.617m	1.725ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.650m	1.237ms	9	10	90.00
V2	lc_escalation	otbn_escalate	25.000s	100.352us	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	17.455us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	46.228us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	92.053us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	38.712us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	256.200us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	256.200us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	35.867us	5	5	100.00
		otbn_csr_rw	6.000s	18.844us	20	20	100.00
		otbn_csr_aliasing	6.000s	14.018us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	25.639us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	35.867us	5	5	100.00
		otbn_csr_rw	6.000s	18.844us	20	20	100.00
		otbn_csr_aliasing	6.000s	14.018us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	25.639us	20	20	100.00
V2		TOTAL			242	246	98.37
V2S	mem_integrity	otbn_imem_err	13.000s	55.276us	10	10	100.00
		otbn_dmem_err	11.000s	107.007us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	1.096ms	5	5	100.00
		otbn_controller_ispr_rdata_err	13.000s	71.828us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	215.777us	5	5	100.00
		otbn_urnd_err	10.000s	69.578us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	24.908us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	24.103us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	28.594us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	8.383m	2.701ms	5	5	100.00
		otbn_tl_intg_err	33.000s	217.222us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.083m	371.045us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	36.782us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	107.007us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	55.276us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	33.000s	217.222us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	25.000s	100.352us	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	55.276us	10	10	100.00
		otbn_dmem_err	11.000s	107.007us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	17.455us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.908us	5	5	100.00
		otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.983m	477.159us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	55.276us	10	10	100.00
		otbn_dmem_err	11.000s	107.007us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	17.455us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.908us	5	5	100.00
		otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	25.000s	100.352us	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	55.276us	10	10	100.00
		otbn_dmem_err	11.000s	107.007us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	17.455us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.908us	5	5	100.00
		otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.983m	477.159us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	34.000s	509.914us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	25.987us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.417m	711.246us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.417m	711.246us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	60.383us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.383m	3.579ms	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	115.743us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	115.743us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	141.786us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.983m	477.159us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.983m	477.159us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.983m	477.159us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	5.617m	1.725ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.983m	477.159us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.983m	477.159us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	21.000s	50.617us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.983m	477.159us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.383m	2.701ms	5	5	100.00
V2S		TOTAL			158	163	96.93
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	32.783m	289.121ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			575	585	98.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	16	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.96	99.61	95.44	99.70	93.49	92.87	100.00	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

1.otbn_stack_addr_integ_chk.105214731934927263712216133003447398529361895394663963872344539263441501007472
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19291581 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19291581 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  19291581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_sec_wipe_err has 2 failures.

3.otbn_sec_wipe_err.15527266990427346439538872757785286469206057963020099866841822102662965393371
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 141786314 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 141786314 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 141786314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_sec_wipe_err.5451529992497932050531644297143252853213475496458312351880421180020455337781
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 54506761 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  54506761 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  54506761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

18.otbn_escalate.33970472503920537222451421672893685285229223993731993678780370490921197525925
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 20516337 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  20516337 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  20516337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.otbn_escalate.101083799074263380338135619372343761968226551265363761758717242795376765280798
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/38.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 27066138 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  27066138 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  27066138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 2.otbn_partial_wipe.21747667607536727544992720184852709100039338412688162847139681580369548539835
    Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 12673428 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  12673428 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  12673428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_stress_all has 1 failures.
  - 4.otbn_stress_all.107039633608042135235692784937161078939244802113857648068890751689009790734696
    Line 332, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all/latest/run.log
```
  UVM_FATAL @ 242696756 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @ 242696756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 9.otbn_rf_base_intg_err.72835252711181447019676133856528707968498256903392901639715308476598721490531
    Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_rf_base_intg_err/latest/run.log
```
  UVM_ERROR @ 199923000 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 199923000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:750) [otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.3191042754930748157342775445160940047872504964895116506974720662248557688859
    Line 339, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 318419207 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 318419207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 43.otbn_escalate.75965352675336977820874385624420288707384028545761527895678057818711684825609
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/43.otbn_escalate/latest/run.log
```
  UVM_FATAL @  56928358 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @  56928358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```