OTBN Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	46.994us	1	1	100.00
V1	single_binary	otbn_single	2.933m	767.374us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	20.772us	5	5	100.00
V1	csr_rw	otbn_csr_rw	5.000s	41.156us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	222.135us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	19.407us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	292.623us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	41.156us	20	20	100.00
		otbn_csr_aliasing	5.000s	19.407us	5	5	100.00
V1	mem_walk	otbn_mem_walk	54.000s	3.896ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	762.421us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	31.000s	162.264us	10	10	100.00
V2	multi_error	otbn_multi_err	48.000s	724.942us	1	1	100.00
V2	back_to_back	otbn_multi	1.317m	162.977us	10	10	100.00
V2	stress_all	otbn_stress_all	1.517m	847.966us	10	10	100.00
V2	lc_escalation	otbn_escalate	29.000s	112.003us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	40.814us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	129.454us	10	10	100.00
V2	alert_test	otbn_alert_test	16.000s	13.915us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	28.079us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	242.635us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	242.635us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	20.772us	5	5	100.00
		otbn_csr_rw	5.000s	41.156us	20	20	100.00
		otbn_csr_aliasing	5.000s	19.407us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	118.521us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	20.772us	5	5	100.00
		otbn_csr_rw	5.000s	41.156us	20	20	100.00
		otbn_csr_aliasing	5.000s	19.407us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	118.521us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	12.000s	76.006us	10	10	100.00
		otbn_dmem_err	13.000s	46.714us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	351.913us	5	5	100.00
		otbn_controller_ispr_rdata_err	14.000s	67.154us	5	5	100.00
		otbn_mac_bignum_acc_err	1.033m	424.727us	5	5	100.00
		otbn_urnd_err	7.000s	21.345us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	19.713us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	45.649us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	69.522us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	13.867m	4.438ms	5	5	100.00
		otbn_tl_intg_err	54.000s	322.987us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	43.000s	948.088us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	46.994us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	46.714us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	76.006us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	54.000s	322.987us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	29.000s	112.003us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	76.006us	10	10	100.00
		otbn_dmem_err	13.000s	46.714us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	40.814us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	19.713us	5	5	100.00
		otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.933m	767.374us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	76.006us	10	10	100.00
		otbn_dmem_err	13.000s	46.714us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	40.814us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	19.713us	5	5	100.00
		otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	29.000s	112.003us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	76.006us	10	10	100.00
		otbn_dmem_err	13.000s	46.714us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	40.814us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	19.713us	5	5	100.00
		otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.933m	767.374us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	13.000s	51.624us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	21.822us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	58.000s	267.703us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	58.000s	267.703us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	28.861us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	84.390us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	39.604us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	39.604us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	28.419us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.933m	767.374us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.933m	767.374us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.933m	767.374us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.317m	162.977us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.933m	767.374us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.933m	767.374us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	21.000s	89.390us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.933m	767.374us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	13.867m	4.438ms	5	5	100.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.767m	2.845ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			579	585	98.97

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	19	95.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.96	99.61	95.49	99.70	93.47	92.75	100.00	98.48	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_sec_wipe_err has 3 failures.

2.otbn_sec_wipe_err.44389828354818398026890903159115429609323945648675901323662220422037248441244
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 30517936 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  30517936 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  30517936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_sec_wipe_err.29099745381933652925750988176137432091397220752066801493264909788257556931984
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 65954072 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  65954072 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  65954072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.103731724965840421138547180978008900750224554915266258177261650877336162470998
    Line 446, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 556434906 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 556434906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.44860404419970716814470424531835386451478072594778230106035028542211672736984
    Line 329, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 175658311 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 175658311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 43.otbn_escalate.18476734308981800356992893872374989265740913394597506455270457735703915083165
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/43.otbn_escalate/latest/run.log
```
  UVM_ERROR @   1633211 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   1633211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```