OTBN Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	15.000s	183.882us	1	1	100.00
V1	single_binary	otbn_single	3.483m	927.263us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	16.164us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	17.087us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	784.976us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	31.837us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	41.513us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	17.087us	20	20	100.00
		otbn_csr_aliasing	7.000s	31.837us	5	5	100.00
V1	mem_walk	otbn_mem_walk	41.000s	1.437ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	21.000s	125.859us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	37.000s	108.726us	10	10	100.00
V2	multi_error	otbn_multi_err	1.567m	388.147us	1	1	100.00
V2	back_to_back	otbn_multi	2.467m	232.615us	10	10	100.00
V2	stress_all	otbn_stress_all	1.650m	308.967us	10	10	100.00
V2	lc_escalation	otbn_escalate	28.000s	75.403us	56	60	93.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	22.512us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	37.931us	10	10	100.00
V2	alert_test	otbn_alert_test	21.000s	25.790us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	23.685us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	175.091us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	175.091us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	16.164us	5	5	100.00
		otbn_csr_rw	6.000s	17.087us	20	20	100.00
		otbn_csr_aliasing	7.000s	31.837us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	55.103us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	16.164us	5	5	100.00
		otbn_csr_rw	6.000s	17.087us	20	20	100.00
		otbn_csr_aliasing	7.000s	31.837us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	55.103us	20	20	100.00
V2		TOTAL			242	246	98.37
V2S	mem_integrity	otbn_imem_err	15.000s	43.641us	10	10	100.00
		otbn_dmem_err	12.000s	31.490us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	202.080us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	345.753us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	215.041us	5	5	100.00
		otbn_urnd_err	6.000s	29.663us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	31.437us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	26.161us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	56.090us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	7.200m	4.643ms	5	5	100.00
		otbn_tl_intg_err	57.000s	365.822us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	47.000s	244.872us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	15.000s	183.882us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	31.490us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	43.641us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	57.000s	365.822us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	28.000s	75.403us	56	60	93.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	43.641us	10	10	100.00
		otbn_dmem_err	12.000s	31.490us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	22.512us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	31.437us	5	5	100.00
		otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	3.483m	927.263us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	43.641us	10	10	100.00
		otbn_dmem_err	12.000s	31.490us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	22.512us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	31.437us	5	5	100.00
		otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	28.000s	75.403us	56	60	93.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	43.641us	10	10	100.00
		otbn_dmem_err	12.000s	31.490us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	22.512us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	31.437us	5	5	100.00
		otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	3.483m	927.263us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	95.421us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	13.000s	49.138us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	39.000s	207.053us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	39.000s	207.053us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	60.632us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	219.851us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	258.762us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	258.762us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	21.548us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	3.483m	927.263us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	3.483m	927.263us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	3.483m	927.263us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.467m	232.615us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	3.483m	927.263us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	3.483m	927.263us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	58.000s	246.435us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	3.483m	927.263us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.200m	4.643ms	5	5	100.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	8.783m	5.001ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			576	585	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.96	99.61	95.49	99.71	93.52	92.76	100.00	98.48	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_sec_wipe_err has 2 failures.

3.otbn_sec_wipe_err.103085618555399924194434860676830344344008748697439267369951429318044958545249
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 6677581 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   6677581 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   6677581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_sec_wipe_err.62994326943018825941632848514478857285536232309024988993302996115443788327810
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 33044753 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  33044753 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  33044753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

38.otbn_escalate.90712213911760643542549322313985185112741963894093330389972426820554244437995
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/38.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 20715638 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  20715638 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  20715638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:

Test otbn_partial_wipe has 1 failures.

0.otbn_partial_wipe.67598260752395921179243701323798786097017314528372706044622858270552845402516
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 3324806 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   3324806 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   3324806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

41.otbn_escalate.6278886034070376089085112036940003910201253722525573773503085322359150575107
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 113606089 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 113606089 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 113606089 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 113606089 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 113606089 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.33159545062139507597848750538393243626536617658734495837014053664234239341230
    Line 602, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1742328610 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1742328610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 8.otbn_rf_base_intg_err.89229415429183757728063013792508595747700395034240898349723858173059994968251
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_rf_base_intg_err/latest/run.log
```
  UVM_ERROR @  33214819 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  33214819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 49.otbn_escalate.24801142626217759242331810471283588097789846442818393566698908322890378910723
    Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/49.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 109938885 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @ 109938885 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @ 109938885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 58.otbn_escalate.6565032131820433879232109448334093888982845097932938942860681509428683058630
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/58.otbn_escalate/latest/run.log
```
  UVM_ERROR @  12727963 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @  12727963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```