OTBN Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	15.000s	45.870us	1	1	100.00
V1	single_binary	otbn_single	42.000s	171.928us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	37.741us	5	5	100.00
V1	csr_rw	otbn_csr_rw	5.000s	48.902us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	534.750us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	17.636us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	184.689us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	48.902us	20	20	100.00
		otbn_csr_aliasing	5.000s	17.636us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.117m	22.134ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	373.548us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	42.000s	176.140us	10	10	100.00
V2	multi_error	otbn_multi_err	51.000s	195.092us	1	1	100.00
V2	back_to_back	otbn_multi	1.650m	518.565us	10	10	100.00
V2	stress_all	otbn_stress_all	2.367m	528.254us	10	10	100.00
V2	lc_escalation	otbn_escalate	24.000s	354.295us	58	60	96.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	47.066us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	2.850m	666.893us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	21.864us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	21.169us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	9.000s	154.482us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	9.000s	154.482us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	37.741us	5	5	100.00
		otbn_csr_rw	5.000s	48.902us	20	20	100.00
		otbn_csr_aliasing	5.000s	17.636us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	43.406us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	37.741us	5	5	100.00
		otbn_csr_rw	5.000s	48.902us	20	20	100.00
		otbn_csr_aliasing	5.000s	17.636us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	43.406us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	16.000s	77.486us	10	10	100.00
		otbn_dmem_err	15.000s	44.836us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	32.789us	5	5	100.00
		otbn_controller_ispr_rdata_err	58.000s	228.832us	5	5	100.00
		otbn_mac_bignum_acc_err	22.000s	143.328us	5	5	100.00
		otbn_urnd_err	7.000s	100.240us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	34.398us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	24.381us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	38.691us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	41.133m	14.750ms	5	5	100.00
		otbn_tl_intg_err	1.283m	523.081us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	49.000s	271.627us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	15.000s	45.870us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	15.000s	44.836us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	77.486us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.283m	523.081us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	24.000s	354.295us	58	60	96.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	77.486us	10	10	100.00
		otbn_dmem_err	15.000s	44.836us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	47.066us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	34.398us	5	5	100.00
		otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	42.000s	171.928us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	77.486us	10	10	100.00
		otbn_dmem_err	15.000s	44.836us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	47.066us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	34.398us	5	5	100.00
		otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	24.000s	354.295us	58	60	96.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	77.486us	10	10	100.00
		otbn_dmem_err	15.000s	44.836us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	47.066us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	34.398us	5	5	100.00
		otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	42.000s	171.928us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	31.682us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	22.724us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	2.283m	461.319us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	2.283m	461.319us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	37.447us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	68.636us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	153.435us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	153.435us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	22.000s	59.002us	2	7	28.57
V2S	sec_cm_data_mem_sec_wipe	otbn_single	42.000s	171.928us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	42.000s	171.928us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	42.000s	171.928us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.650m	518.565us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	42.000s	171.928us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	42.000s	171.928us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	32.000s	122.067us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	42.000s	171.928us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	41.133m	14.750ms	5	5	100.00
V2S		TOTAL			155	163	95.09
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	23.250m	18.689ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			574	585	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.91	99.62	95.58	99.70	93.58	92.72	97.44	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

0.otbn_stack_addr_integ_chk.23917739462756084313290544176841105827533055394228815015652543093074856756853
Line 297, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14192744 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 14192744 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  14192744 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  14192744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_sec_wipe_err has 4 failures.

1.otbn_sec_wipe_err.53002490616588329695396185361716277754605823548160759710558130805409721092957
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 141240397 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 141240397 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 141240397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_wipe_err.75928079065103470951774759041477206898204793330909772680253185436448403263593
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 59002314 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  59002314 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  59002314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 4.otbn_sec_wipe_err.112383896985214067125141103939997745995356541701348008265127569139570603286077
    Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 15064981 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  15064981 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  15064981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otbn_partial_wipe has 1 failures.
  - 8.otbn_partial_wipe.57566107058559460032127425210868711475942440730712627339667575182898570765572
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 4607045 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   4607045 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   4607045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 2.otbn_partial_wipe.82839578929994103563025761788917651483269449604782169961771602752405514454384
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 16504112 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  16504112 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  16504112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.68177120036651370093353150699196390557456150451022599014498621665909352734560
    Line 406, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1201217650 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1201217650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 16.otbn_escalate.12522541559823682288988772287618033287390716630968998208449952014482526687311
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log
```
  UVM_FATAL @ 164449878 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @ 164449878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 29.otbn_escalate.12283668588343153680665332179767643603776263662643969830235767544517608580883
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_escalate/latest/run.log
```
  UVM_ERROR @   5885524 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   5885524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```