OTBN Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	84.032us	1	1	100.00
V1	single_binary	otbn_single	5.350m	1.641ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	21.069us	5	5	100.00
V1	csr_rw	otbn_csr_rw	8.000s	29.148us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	55.353us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	20.332us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	60.223us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	8.000s	29.148us	20	20	100.00
		otbn_csr_aliasing	5.000s	20.332us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.050m	10.503ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	474.848us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	38.000s	132.359us	10	10	100.00
V2	multi_error	otbn_multi_err	45.000s	545.674us	1	1	100.00
V2	back_to_back	otbn_multi	8.250m	2.155ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.833m	2.945ms	10	10	100.00
V2	lc_escalation	otbn_escalate	55.000s	236.903us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	65.553us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	20.000s	54.673us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	18.063us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	33.769us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	13.000s	701.267us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	13.000s	701.267us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	21.069us	5	5	100.00
		otbn_csr_rw	8.000s	29.148us	20	20	100.00
		otbn_csr_aliasing	5.000s	20.332us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	48.594us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	21.069us	5	5	100.00
		otbn_csr_rw	8.000s	29.148us	20	20	100.00
		otbn_csr_aliasing	5.000s	20.332us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	48.594us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	12.000s	43.939us	10	10	100.00
		otbn_dmem_err	32.000s	131.511us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	15.000s	68.174us	5	5	100.00
		otbn_controller_ispr_rdata_err	15.000s	77.990us	5	5	100.00
		otbn_mac_bignum_acc_err	16.000s	139.824us	5	5	100.00
		otbn_urnd_err	7.000s	18.199us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	68.775us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	39.078us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	27.870us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	6.683m	2.152ms	5	5	100.00
		otbn_tl_intg_err	41.000s	259.350us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	59.000s	337.754us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	84.032us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	32.000s	131.511us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	43.939us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	41.000s	259.350us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	55.000s	236.903us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	43.939us	10	10	100.00
		otbn_dmem_err	32.000s	131.511us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	65.553us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	68.775us	5	5	100.00
		otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	5.350m	1.641ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	43.939us	10	10	100.00
		otbn_dmem_err	32.000s	131.511us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	65.553us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	68.775us	5	5	100.00
		otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	55.000s	236.903us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	43.939us	10	10	100.00
		otbn_dmem_err	32.000s	131.511us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	65.553us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	68.775us	5	5	100.00
		otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	5.350m	1.641ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	32.205us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	25.984us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	33.000s	296.025us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	33.000s	296.025us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	30.320us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	19.000s	42.896us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	92.211us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	92.211us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	19.590us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	5.350m	1.641ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	5.350m	1.641ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	5.350m	1.641ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	8.250m	2.155ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	5.350m	1.641ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	5.350m	1.641ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	39.314us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	5.350m	1.641ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.683m	2.152ms	5	5	100.00
V2S		TOTAL			162	163	99.39
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	14.133m	8.144ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			581	585	99.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	19	95.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.93	99.60	95.40	99.69	93.41	92.57	100.00	98.83	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:750) [otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.34638251798367082494251291681142994998373643005260979095212839113515570188550
    Line 559, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4070294635 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4070294635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.71556439421694528550661345420978196750211698669979655875905480571539729993728
    Line 631, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3676209461 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3676209461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 9.otbn_partial_wipe.36217393935800444282535124395859152960187160839409625693886461145422475419663
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 10256317 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  10256317 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  10256317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 48.otbn_escalate.104062856749418986202335673238314047012651649340790261950807228674689615169695
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/48.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 51311339 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  51311339 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  51311339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTBN Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `aad711e1bc`