OTBN Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	138.530us	1	1	100.00
V1	single_binary	otbn_single	14.833m	7.956ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	24.048us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	13.723us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	61.601us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	24.568us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	60.937us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	13.723us	20	20	100.00
		otbn_csr_aliasing	7.000s	24.568us	5	5	100.00
V1	mem_walk	otbn_mem_walk	50.000s	1.196ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	1.459ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	44.000s	95.751us	10	10	100.00
V2	multi_error	otbn_multi_err	43.000s	208.794us	1	1	100.00
V2	back_to_back	otbn_multi	2.600m	480.714us	10	10	100.00
V2	stress_all	otbn_stress_all	2.067m	580.148us	10	10	100.00
V2	lc_escalation	otbn_escalate	37.000s	125.214us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	67.524us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	38.000s	630.483us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	33.243us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	49.526us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	399.899us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	399.899us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	24.048us	5	5	100.00
		otbn_csr_rw	6.000s	13.723us	20	20	100.00
		otbn_csr_aliasing	7.000s	24.568us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	29.965us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	24.048us	5	5	100.00
		otbn_csr_rw	6.000s	13.723us	20	20	100.00
		otbn_csr_aliasing	7.000s	24.568us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	29.965us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	11.000s	24.622us	10	10	100.00
		otbn_dmem_err	12.000s	165.810us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	40.207us	5	5	100.00
		otbn_controller_ispr_rdata_err	1.217m	316.723us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	57.620us	5	5	100.00
		otbn_urnd_err	8.000s	15.220us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	24.813us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	315.526us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	70.562us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	10.633m	3.614ms	5	5	100.00
		otbn_tl_intg_err	1.233m	472.563us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	40.000s	228.106us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	138.530us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	165.810us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	24.622us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.233m	472.563us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	37.000s	125.214us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	24.622us	10	10	100.00
		otbn_dmem_err	12.000s	165.810us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	67.524us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.813us	5	5	100.00
		otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	14.833m	7.956ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	24.622us	10	10	100.00
		otbn_dmem_err	12.000s	165.810us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	67.524us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.813us	5	5	100.00
		otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	37.000s	125.214us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	24.622us	10	10	100.00
		otbn_dmem_err	12.000s	165.810us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	67.524us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.813us	5	5	100.00
		otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	14.833m	7.956ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	26.820us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	44.419us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	53.000s	343.589us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	53.000s	343.589us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	42.649us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	64.606us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	71.151us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	71.151us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	23.916us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	14.833m	7.956ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	14.833m	7.956ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	14.833m	7.956ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.600m	480.714us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	14.833m	7.956ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	14.833m	7.956ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	57.384us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	14.833m	7.956ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	10.633m	3.614ms	5	5	100.00
V2S		TOTAL			158	163	96.93
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	50.283m	10.509ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			575	585	98.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.89	99.60	95.40	99.69	93.47	92.66	97.44	91.14	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_sec_wipe_err has 3 failures.

0.otbn_sec_wipe_err.88761146344513273225452166023598174343478332599637557971738105501418867470004
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 70669598 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  70669598 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  70669598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_wipe_err.26918650499686056339963391778287095412203160057041733211078448439776940951058
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23916154 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  23916154 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  23916154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otbn_escalate has 1 failures.

32.otbn_escalate.30883761288981077168130148896087618047236935185091247428026820852085192044221
Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/32.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19031449 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19031449 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  19031449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.53711782254606891992775723936620538086874581595488766275042152404552806363415
    Line 668, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11414063165 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11414063165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otbn_stress_all_with_rand_reset.37584054144859579302641572972189219759344634711788029810838794506992298923089
    Line 338, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 438884334 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 438884334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:

Test otbn_partial_wipe has 2 failures.

2.otbn_partial_wipe.67750979023661325119472087457109248598444450078507362786734708103078450557654
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 14505235 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  14505235 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  14505235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_partial_wipe.66537011134662863544635518551905391143678703068491641614576350094534069119877
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 15498162 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  15498162 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  15498162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.97400301476838694454403743179267976533812459125312847492216230952109603375147
    Line 318, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  27094192 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  27094192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:486) [otbn_dmem_err_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.24895305834276828902126258966955056543556659050278070765049378899012937740806
    Line 607, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10509447559 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 10509447559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```