OTBN Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	110.629us	1	1	100.00
V1	single_binary	otbn_single	1.417m	342.360us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	9.000s	54.324us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	42.518us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	501.456us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	9.000s	42.527us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	72.893us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	42.518us	20	20	100.00
		otbn_csr_aliasing	9.000s	42.527us	5	5	100.00
V1	mem_walk	otbn_mem_walk	47.000s	1.220ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	20.000s	448.025us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	36.000s	143.048us	10	10	100.00
V2	multi_error	otbn_multi_err	52.000s	162.799us	1	1	100.00
V2	back_to_back	otbn_multi	1.883m	1.469ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.200m	421.628us	10	10	100.00
V2	lc_escalation	otbn_escalate	20.000s	122.276us	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	19.111us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	16.000s	26.288us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	31.136us	50	50	100.00
V2	intr_test	otbn_intr_test	11.000s	58.756us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	14.000s	38.837us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	14.000s	38.837us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	9.000s	54.324us	5	5	100.00
		otbn_csr_rw	10.000s	42.518us	20	20	100.00
		otbn_csr_aliasing	9.000s	42.527us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	27.247us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	9.000s	54.324us	5	5	100.00
		otbn_csr_rw	10.000s	42.518us	20	20	100.00
		otbn_csr_aliasing	9.000s	42.527us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	27.247us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	17.000s	66.498us	10	10	100.00
		otbn_dmem_err	16.000s	17.784us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	46.000s	176.709us	5	5	100.00
		otbn_controller_ispr_rdata_err	30.000s	107.611us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	18.883us	5	5	100.00
		otbn_urnd_err	8.000s	20.822us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	28.563us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	13.000s	40.701us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	22.168us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	21.000m	7.997ms	5	5	100.00
		otbn_tl_intg_err	34.000s	189.312us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	41.000s	367.258us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	110.629us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	17.784us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	17.000s	66.498us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	34.000s	189.312us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	20.000s	122.276us	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	17.000s	66.498us	10	10	100.00
		otbn_dmem_err	16.000s	17.784us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	19.111us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	28.563us	5	5	100.00
		otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.417m	342.360us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	17.000s	66.498us	10	10	100.00
		otbn_dmem_err	16.000s	17.784us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	19.111us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	28.563us	5	5	100.00
		otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	20.000s	122.276us	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	17.000s	66.498us	10	10	100.00
		otbn_dmem_err	16.000s	17.784us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	19.111us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	28.563us	5	5	100.00
		otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.417m	342.360us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	20.000s	72.338us	10	12	83.33
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	60.734us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.600m	1.935ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.600m	1.935ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	21.563us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	232.524us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	23.000s	343.547us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	23.000s	343.547us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	17.000s	19.998us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.417m	342.360us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.417m	342.360us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.417m	342.360us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.883m	1.469ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.417m	342.360us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.417m	342.360us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	19.000s	37.644us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.417m	342.360us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	21.000m	7.997ms	5	5	100.00
V2S		TOTAL			158	163	96.93
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.039h	15.443ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			573	585	97.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.96	99.62	95.67	99.71	93.67	92.46	100.00	98.72	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_sec_wipe_err has 3 failures.

2.otbn_sec_wipe_err.35053125021742046012910505951697304527433128006745419461251308798043758495481
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 9361433 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   9361433 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   9361433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_wipe_err.16126752769135555026149479031682058131198802190004670630301375125802994717350
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19998317 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19998317 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  19998317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otbn_ctrl_redun has 2 failures.

7.otbn_ctrl_redun.23516573914744554117165558191909478140153898779521470622622978063047325694491
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8268818 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 8268818 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   8268818 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   8268818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.otbn_ctrl_redun.108382387573524391415809629518683110312019862924851536927684424337162465593793
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 287005042 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 287005042 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @ 287005042 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 287005042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 2.otbn_stress_all_with_rand_reset.35892871022046002953231690503296114759127815200390002672544406976102223480378
    Line 535, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15442654225 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15442654225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otbn_stress_all_with_rand_reset.15584377498586458331164787270166943562540706771668152451973411451818434259826
    Line 520, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2770678087 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2770678087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 3 failures:

Test otbn_escalate has 3 failures.

32.otbn_escalate.51041173581633173536066479614732745591600427654234152763109894968362786966220
Line 296, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/32.otbn_escalate/latest/run.log

  UVM_ERROR @  17558703 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (255 [0xff] vs 4 [0x4]) value for register otbn_reg_block.status
  UVM_INFO @  17558703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.otbn_escalate.36805704671869241493190371161873610467467993326418102679441610406732021995905
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/46.otbn_escalate/latest/run.log

  UVM_ERROR @   4669609 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   4669609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.42276585688575654228590423882202669509577799376385078830458184259345663127399
    Line 556, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7251717623 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7251717623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```