OTBN Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	325.012us	1	1	100.00
V1	single_binary	otbn_single	43.000s	180.215us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	34.294us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	17.464us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	140.138us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	35.279us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	41.187us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	17.464us	20	20	100.00
		otbn_csr_aliasing	5.000s	35.279us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.033m	22.247ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	17.000s	1.351ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	50.000s	206.323us	10	10	100.00
V2	multi_error	otbn_multi_err	47.000s	308.006us	1	1	100.00
V2	back_to_back	otbn_multi	19.317m	4.941ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.117m	459.412us	10	10	100.00
V2	lc_escalation	otbn_escalate	49.000s	191.304us	50	60	83.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	24.601us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	26.000s	56.835us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	16.298us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	23.110us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	470.452us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	470.452us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	34.294us	5	5	100.00
		otbn_csr_rw	6.000s	17.464us	20	20	100.00
		otbn_csr_aliasing	5.000s	35.279us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	26.362us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	34.294us	5	5	100.00
		otbn_csr_rw	6.000s	17.464us	20	20	100.00
		otbn_csr_aliasing	5.000s	35.279us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	26.362us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	13.000s	35.352us	10	10	100.00
		otbn_dmem_err	12.000s	38.096us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	62.489us	5	5	100.00
		otbn_controller_ispr_rdata_err	14.000s	67.641us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	230.477us	5	5	100.00
		otbn_urnd_err	7.000s	34.757us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	13.000s	57.879us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	37.962us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	40.033us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	6.717m	5.245ms	2	5	40.00
		otbn_tl_intg_err	49.000s	328.305us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	41.000s	245.323us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	325.012us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	38.096us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	35.352us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	49.000s	328.305us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	49.000s	191.304us	50	60	83.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	35.352us	10	10	100.00
		otbn_dmem_err	12.000s	38.096us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	24.601us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	57.879us	5	5	100.00
		otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	43.000s	180.215us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	35.352us	10	10	100.00
		otbn_dmem_err	12.000s	38.096us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	24.601us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	57.879us	5	5	100.00
		otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	49.000s	191.304us	50	60	83.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	35.352us	10	10	100.00
		otbn_dmem_err	12.000s	38.096us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	24.601us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	57.879us	5	5	100.00
		otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	43.000s	180.215us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	13.000s	55.133us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	38.344us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	43.000s	149.599us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	43.000s	149.599us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	1.183m	2.016ms	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	121.442us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	106.474us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	106.474us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	76.265us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	43.000s	180.215us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	43.000s	180.215us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	43.000s	180.215us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	19.317m	4.941ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	43.000s	180.215us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	43.000s	180.215us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	48.693us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	43.000s	180.215us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.717m	5.245ms	2	5	40.00
V2S		TOTAL			157	163	96.32
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	15.400m	4.965ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			565	585	96.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	16	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.96	99.60	95.40	99.70	93.55	92.80	100.00	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 10 failures:

Test otbn_escalate has 9 failures.

0.otbn_escalate.104322777742805821183791292832170937267191768556072337594791438065652525768399
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17545939 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  17545939 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  17545939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.otbn_escalate.54526131355886039529020511537279224938158524233755141152800580592703274239047
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 38621248 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  38621248 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  38621248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test otbn_ctrl_redun has 1 failures.

0.otbn_ctrl_redun.6455846477423534190675827577178388835708290537015427763865574789219391673357
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22050166 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 22050166 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  22050166 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  22050166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

1.otbn_sec_cm.9834434312284239189011051763664934612206807594206454811760178952446035097993
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 225603412 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 225603412 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 225603412 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 225603412 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 225603412 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

2.otbn_sec_cm.23091477217181072646070480589385640147019102059074500848165137203287902598028
Line 268, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 31360156 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 31360156 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 31360156 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 31360156 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 31360156 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:390) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 0.otbn_rf_base_intg_err.29884662924825977038794472857869341167832016234520587481232038606338624218420
    Line 294, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 2015760531 ps: (csr_utils_pkg.sv:390) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x87990018)
  UVM_INFO @ 2015760531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 0.otbn_sec_wipe_err.20199807711537044088671114606896661273669152299603494776064130033268993393097
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 14448727 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  14448727 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  14448727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.16021403512735358443899097366494593858091264405454359024011194370512860370446
    Line 320, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  23915608 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  23915608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.41687107228079847494570428206307456157242594236233512796296536200992725537782
    Line 388, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4964997186 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 4964997186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.19754229835027010037542139522491145925145708786452196355637509757805874352814
    Line 468, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2494459239 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2494459239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:486) [otbn_single_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.89137861200473697136421034849337593138211573051848837712863973898619674931414
    Line 364, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10055367335 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 10055367335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 25.otbn_escalate.24183586345303156690468940454561816256576427146111840278895395950505417965700
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log
```
  UVM_ERROR @  11185476 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @  11185476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```