OTBN Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	38.979us	1	1	100.00
V1	single_binary	otbn_single	1.667m	431.897us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	15.000s	18.010us	5	5	100.00
V1	csr_rw	otbn_csr_rw	11.000s	12.883us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	35.515us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	10.000s	31.161us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	26.599us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	11.000s	12.883us	20	20	100.00
		otbn_csr_aliasing	10.000s	31.161us	5	5	100.00
V1	mem_walk	otbn_mem_walk	55.000s	4.968ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	27.000s	3.183ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	42.000s	163.926us	10	10	100.00
V2	multi_error	otbn_multi_err	1.017m	265.701us	1	1	100.00
V2	back_to_back	otbn_multi	1.367m	193.119us	10	10	100.00
V2	stress_all	otbn_stress_all	1.800m	400.348us	10	10	100.00
V2	lc_escalation	otbn_escalate	21.000s	359.612us	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	54.422us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	37.440us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	36.092us	50	50	100.00
V2	intr_test	otbn_intr_test	11.000s	23.296us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	110.579us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	110.579us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	15.000s	18.010us	5	5	100.00
		otbn_csr_rw	11.000s	12.883us	20	20	100.00
		otbn_csr_aliasing	10.000s	31.161us	5	5	100.00
		otbn_same_csr_outstanding	15.000s	26.987us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	15.000s	18.010us	5	5	100.00
		otbn_csr_rw	11.000s	12.883us	20	20	100.00
		otbn_csr_aliasing	10.000s	31.161us	5	5	100.00
		otbn_same_csr_outstanding	15.000s	26.987us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	12.000s	244.521us	10	10	100.00
		otbn_dmem_err	14.000s	144.205us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	37.942us	5	5	100.00
		otbn_controller_ispr_rdata_err	14.000s	54.141us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	42.119us	5	5	100.00
		otbn_urnd_err	10.000s	31.231us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	65.040us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	43.679us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	28.946us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	6.183m	3.430ms	2	5	40.00
		otbn_tl_intg_err	41.000s	265.416us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	57.000s	291.513us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	38.979us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	14.000s	144.205us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	244.521us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	41.000s	265.416us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	21.000s	359.612us	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	244.521us	10	10	100.00
		otbn_dmem_err	14.000s	144.205us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	54.422us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	65.040us	5	5	100.00
		otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.667m	431.897us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	244.521us	10	10	100.00
		otbn_dmem_err	14.000s	144.205us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	54.422us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	65.040us	5	5	100.00
		otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	21.000s	359.612us	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	244.521us	10	10	100.00
		otbn_dmem_err	14.000s	144.205us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	54.422us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	65.040us	5	5	100.00
		otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.667m	431.897us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	39.981us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	29.021us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.550m	540.293us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.550m	540.293us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	26.000s	2.034ms	8	10	80.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	92.523us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	55.351us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	55.351us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	18.000s	109.801us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.667m	431.897us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.667m	431.897us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.667m	431.897us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.367m	193.119us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.667m	431.897us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.667m	431.897us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	24.000s	156.137us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.667m	431.897us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.183m	3.430ms	2	5	40.00
V2S		TOTAL			156	163	95.71
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	32.233m	10.192ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			570	585	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.93	99.61	95.49	99.71	93.64	92.25	100.00	98.37	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.52718265904500381817215705960706984675505153276915027380406598638348233012212
Line 305, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 49188478 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 49188478 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 49188478 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 49188478 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 49188478 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.8353021162285634806366570948853826730618952508134336721608018421939936798361
Line 357, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 174875523 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 174875523 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 174875523 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 174875523 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 174875523 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

37.otbn_escalate.34567321499760295222072363997478178469693175994126475645147401872169934032587
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/37.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 71031363 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  71031363 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  71031363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.otbn_escalate.74231720042420652520629371309925199341646555027704223731051197683339262935640
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/43.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32690097 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  32690097 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  32690097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 2.otbn_stress_all_with_rand_reset.15107502514414183216281134061192237737759526823152998213993702623990085267689
    Line 352, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1138669519 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1138669519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otbn_stress_all_with_rand_reset.18582441984732311250086860497812829582119394627616734932567727079439385949430
    Line 347, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 524323235 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 524323235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 8.otbn_stress_all_with_rand_reset.54889356842722816000273960906042560144915876858884635165203885357871208977565
    Line 852, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 116879823432 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 116879823432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otbn_stress_all_with_rand_reset.78264746172438585290578699070235067002735284559197333877902709079946468087766
    Line 336, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 176745024 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 176745024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 0.otbn_partial_wipe.84910223709820829179811991795225590114060524905505997753974128721384671584515
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 7330457 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   7330457 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   7330457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:486) [otbn_single_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.38024300526619036287360024664016016047723817320771450869103019554120775619101
    Line 446, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10192213663 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 10192213663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 4.otbn_partial_wipe.41641875089158416406289099627404388398005730624197047667324656177190559125862
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 7158583 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   7158583 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   7158583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:222) [csr_utils::csr_wr] Timeout waiting to csr_wr otbn_reg_block.err_bits (addr=*) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 6.otbn_rf_base_intg_err.30067229023823422123834035957875805760835454108956427830405059822076893325723
    Line 294, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 2065573424 ps: (csr_utils_pkg.sv:222) [csr_utils::csr_wr] Timeout waiting to csr_wr otbn_reg_block.err_bits (addr=0x999c001c)
  UVM_INFO @ 2065573424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:390) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 7.otbn_rf_base_intg_err.97582971312990416376820952219219664533669684085624380273325545204993106512282
    Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 2034375201 ps: (csr_utils_pkg.sv:390) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0xd0850018)
  UVM_INFO @ 2034375201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```