OTBN Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	157.423us	1	1	100.00
V1	single_binary	otbn_single	25.000s	78.515us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	14.419us	5	5	100.00
V1	csr_rw	otbn_csr_rw	5.000s	16.228us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	253.871us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	46.534us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	151.567us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	16.228us	20	20	100.00
		otbn_csr_aliasing	6.000s	46.534us	5	5	100.00
V1	mem_walk	otbn_mem_walk	56.000s	7.779ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	435.072us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	59.000s	285.584us	10	10	100.00
V2	multi_error	otbn_multi_err	49.000s	878.049us	1	1	100.00
V2	back_to_back	otbn_multi	21.867m	11.371ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.733m	319.410us	10	10	100.00
V2	lc_escalation	otbn_escalate	1.467m	1.723ms	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	28.734us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	116.232us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	32.644us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	42.175us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	90.042us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	90.042us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	14.419us	5	5	100.00
		otbn_csr_rw	5.000s	16.228us	20	20	100.00
		otbn_csr_aliasing	6.000s	46.534us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	45.102us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	14.419us	5	5	100.00
		otbn_csr_rw	5.000s	16.228us	20	20	100.00
		otbn_csr_aliasing	6.000s	46.534us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	45.102us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	13.000s	25.095us	10	10	100.00
		otbn_dmem_err	13.000s	36.956us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	28.000s	87.278us	5	5	100.00
		otbn_controller_ispr_rdata_err	10.000s	55.480us	5	5	100.00
		otbn_mac_bignum_acc_err	15.000s	41.174us	5	5	100.00
		otbn_urnd_err	8.000s	52.218us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	35.740us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	19.192us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	52.421us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	6.883m	2.790ms	4	5	80.00
		otbn_tl_intg_err	32.000s	187.159us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	43.000s	238.778us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	157.423us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	36.956us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	25.095us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	32.000s	187.159us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.467m	1.723ms	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	25.095us	10	10	100.00
		otbn_dmem_err	13.000s	36.956us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	28.734us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	35.740us	5	5	100.00
		otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	25.000s	78.515us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	25.095us	10	10	100.00
		otbn_dmem_err	13.000s	36.956us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	28.734us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	35.740us	5	5	100.00
		otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.467m	1.723ms	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	25.095us	10	10	100.00
		otbn_dmem_err	13.000s	36.956us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	28.734us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	35.740us	5	5	100.00
		otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	25.000s	78.515us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	80.396us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	46.402us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.317m	229.655us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.317m	229.655us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	30.674us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	241.816us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	19.000s	201.034us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	19.000s	201.034us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	24.000s	106.262us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	25.000s	78.515us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	25.000s	78.515us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	25.000s	78.515us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	21.867m	11.371ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	25.000s	78.515us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	25.000s	78.515us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	13.000s	48.379us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	25.000s	78.515us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.883m	2.790ms	4	5	80.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	17.533m	3.719ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			576	585	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.95	99.61	95.53	99.69	93.55	92.71	100.00	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:
- Test otbn_partial_wipe has 1 failures.
  - 5.otbn_partial_wipe.87432226058033976861825394083733633426458811830574390266151028495648033681133
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 3608372 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   3608372 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   3608372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otbn_sec_wipe_err has 1 failures.
  - 6.otbn_sec_wipe_err.75809010000010897297063663123395003433815945171467874558527447122021792167507
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 106505723 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @ 106505723 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @ 106505723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_escalate has 2 failures.

19.otbn_escalate.62391972461703591220101493780026471040484617725188345957822172146648070225594
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 85322020 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  85322020 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  85322020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.otbn_escalate.49537138611600501480539806463873626149279230970996083000614925619489767192636
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/48.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 59833458 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  59833458 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  59833458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.44569476449586869562020026187248446379266350054736764491013096964858656606483
Line 304, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 681789785 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 681789785 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 681789785 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 681789785 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 681789785 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.44644384981719283710206712704108377656659953061955817879828992783784088908983
    Line 320, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  22975227 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  22975227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.61448341399889961524629466589783290557226679018480552059724849787124491304883
    Line 686, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3718647244 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3718647244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:390) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.err_bits (addr=*) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.105761923695115174887709564995084911854556869220763831546068335978189150968324
    Line 758, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5174774874 ps: (csr_utils_pkg.sv:390) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.err_bits (addr=0x2b001c)
  UVM_INFO @ 5174774874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 47.otbn_escalate.80083720972905738633939961268243885067628276754922385837994593496086243806253
    Line 316, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/47.otbn_escalate/latest/run.log
```
  UVM_ERROR @  11785542 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (255 [0xff] vs 4 [0x4]) value for register otbn_reg_block.status
  UVM_INFO @  11785542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```