OTBN Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	73.554us	1	1	100.00
V1	single_binary	otbn_single	55.000s	386.443us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	21.677us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	26.821us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	131.545us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	46.965us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	43.793us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	26.821us	20	20	100.00
		otbn_csr_aliasing	5.000s	46.965us	5	5	100.00
V1	mem_walk	otbn_mem_walk	31.000s	369.281us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	8.140ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	2.233m	696.110us	10	10	100.00
V2	multi_error	otbn_multi_err	1.233m	219.651us	1	1	100.00
V2	back_to_back	otbn_multi	7.767m	5.258ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.600m	1.493ms	10	10	100.00
V2	lc_escalation	otbn_escalate	10.033m	2.889ms	56	60	93.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	16.551us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	23.000s	67.340us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	20.250us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	23.275us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	107.560us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	107.560us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	21.677us	5	5	100.00
		otbn_csr_rw	7.000s	26.821us	20	20	100.00
		otbn_csr_aliasing	5.000s	46.965us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	24.686us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	21.677us	5	5	100.00
		otbn_csr_rw	7.000s	26.821us	20	20	100.00
		otbn_csr_aliasing	5.000s	46.965us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	24.686us	20	20	100.00
V2		TOTAL			241	246	97.97
V2S	mem_integrity	otbn_imem_err	11.000s	26.414us	10	10	100.00
		otbn_dmem_err	46.000s	496.034us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	28.000s	663.590us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	139.605us	5	5	100.00
		otbn_mac_bignum_acc_err	20.000s	148.504us	5	5	100.00
		otbn_urnd_err	8.000s	14.322us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	41.770us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	29.478us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	48.212us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	8.033m	20.658ms	4	5	80.00
		otbn_tl_intg_err	1.267m	493.267us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	41.000s	222.081us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	73.554us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	46.000s	496.034us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	26.414us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.267m	493.267us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	10.033m	2.889ms	56	60	93.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	26.414us	10	10	100.00
		otbn_dmem_err	46.000s	496.034us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	16.551us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	41.770us	5	5	100.00
		otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	55.000s	386.443us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	26.414us	10	10	100.00
		otbn_dmem_err	46.000s	496.034us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	16.551us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	41.770us	5	5	100.00
		otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	10.033m	2.889ms	56	60	93.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	26.414us	10	10	100.00
		otbn_dmem_err	46.000s	496.034us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	16.551us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	41.770us	5	5	100.00
		otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	55.000s	386.443us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	30.644us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	230.492us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	34.000s	82.390us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	34.000s	82.390us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	34.622us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	45.361us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	25.000s	170.271us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	25.000s	170.271us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	34.558us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	55.000s	386.443us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	55.000s	386.443us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	55.000s	386.443us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	7.767m	5.258ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	55.000s	386.443us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	55.000s	386.443us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	15.000s	90.818us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	55.000s	386.443us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.033m	20.658ms	4	5	80.00
V2S		TOTAL			162	163	99.39
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	29.083m	8.232ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			576	585	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	19	95.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.95	99.61	95.53	99.70	93.52	92.57	100.00	98.72	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_zero_state_err_urnd has 1 failures.

3.otbn_zero_state_err_urnd.88547434706021916398936150060579969838955860485353150894429893343395253988262
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 18821995 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  18821995 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  18821995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

11.otbn_escalate.91458966858020956711083138293732139808800796009631956270317607760204721408061
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 51287313 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  51287313 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  51287313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

55.otbn_escalate.18138274530207623892687129207816164039717418590294829878425835607916793453414
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/55.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 36724245 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  36724245 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  36724245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 5.otbn_stress_all_with_rand_reset.79272426237322041980427851616552537617081635917636553223151963212676852389503
    Line 506, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10329631512 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10329631512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otbn_stress_all_with_rand_reset.78135019366565376043795718489469197691766428952173315710625947450688614838642
    Line 464, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1516956727 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1516956727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.7816160662440509827492234582476986036061446762040403332184066205387391855171
    Line 352, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3254275113 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3254275113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

3.otbn_sec_cm.90451192592423358889097744035013347847650916879283305314745950067338788693834
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 97949630 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 97949630 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 97949630 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 97949630 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 97949630 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 22.otbn_escalate.33431534214406193846747200020252135593257793094931045008902219538362606185191
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log
```
  UVM_FATAL @  99228126 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @  99228126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 31.otbn_escalate.78411215732483987843370843783992649151201680376383326088167206152335165544183
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/31.otbn_escalate/latest/run.log
```
  UVM_ERROR @   6454331 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   6454331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```