OTBN Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	256.324us	1	1	100.00
V1	single_binary	otbn_single	36.000s	114.191us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	34.750us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	22.010us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	270.854us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	32.139us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	42.471us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	22.010us	20	20	100.00
		otbn_csr_aliasing	5.000s	32.139us	5	5	100.00
V1	mem_walk	otbn_mem_walk	54.000s	4.418ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	466.757us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	45.000s	205.376us	10	10	100.00
V2	multi_error	otbn_multi_err	48.000s	260.486us	1	1	100.00
V2	back_to_back	otbn_multi	1.417m	1.330ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.917m	583.734us	10	10	100.00
V2	lc_escalation	otbn_escalate	32.000s	123.766us	53	60	88.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	67.704us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	24.000s	171.798us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	14.285us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	27.668us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	553.673us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	553.673us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	34.750us	5	5	100.00
		otbn_csr_rw	7.000s	22.010us	20	20	100.00
		otbn_csr_aliasing	5.000s	32.139us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	42.904us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	34.750us	5	5	100.00
		otbn_csr_rw	7.000s	22.010us	20	20	100.00
		otbn_csr_aliasing	5.000s	32.139us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	42.904us	20	20	100.00
V2		TOTAL			239	246	97.15
V2S	mem_integrity	otbn_imem_err	15.000s	109.343us	10	10	100.00
		otbn_dmem_err	18.000s	72.127us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	64.638us	5	5	100.00
		otbn_controller_ispr_rdata_err	24.000s	80.232us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	91.778us	5	5	100.00
		otbn_urnd_err	6.000s	9.589us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	20.141us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	14.000s	56.029us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	25.340us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	7.500m	1.889ms	2	5	40.00
		otbn_tl_intg_err	46.000s	306.694us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	59.000s	336.349us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	256.324us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	18.000s	72.127us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	109.343us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	46.000s	306.694us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	32.000s	123.766us	53	60	88.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	109.343us	10	10	100.00
		otbn_dmem_err	18.000s	72.127us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	67.704us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	20.141us	5	5	100.00
		otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	36.000s	114.191us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	109.343us	10	10	100.00
		otbn_dmem_err	18.000s	72.127us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	67.704us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	20.141us	5	5	100.00
		otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	32.000s	123.766us	53	60	88.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	109.343us	10	10	100.00
		otbn_dmem_err	18.000s	72.127us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	67.704us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	20.141us	5	5	100.00
		otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	36.000s	114.191us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	37.595us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	35.288us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	45.000s	663.657us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	45.000s	663.657us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	19.355us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	25.000s	95.375us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	117.758us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	117.758us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	61.624us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	36.000s	114.191us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	36.000s	114.191us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	36.000s	114.191us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.417m	1.330ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	36.000s	114.191us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	36.000s	114.191us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	30.000s	512.601us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	36.000s	114.191us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.500m	1.889ms	2	5	40.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	21.083m	7.730ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			572	585	97.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.93	99.62	95.58	99.70	93.47	93.16	97.44	91.26	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 6 failures:

Test otbn_escalate has 6 failures.

5.otbn_escalate.97093166834962476388201172127487072220708501481291007928724003222307759223951
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 11008715 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  11008715 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  11008715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.otbn_escalate.12795670720995310594705755676161641198218787808752833628787907656416083990946
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 48574328 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  48574328 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  48574328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.63495637690803331446078231944136043078938846755619039352564574704415308438401
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 126555599 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 126555599 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 126555599 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 126555599 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 126555599 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.110837140170889423679998016831436142138052618229079981896462494562752134521584
Line 266, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 14903760 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 14903760 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 14903760 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 14903760 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 14903760 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.35514569018778910964986407511542406783416577556032196206945323067974858673174
    Line 445, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7730168488 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7730168488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.29643159609232432357241057709934022951133029451360850221933152712655688024163
    Line 337, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 725179484 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 725179484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 9.otbn_partial_wipe.22962677357860505044604633543691265262594896008733845898314878950154604729388
    Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 12483542 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  12483542 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  12483542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 22.otbn_escalate.64700676728434423955678545461362254418871213597721769981260457631993671777382
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log
```
  UVM_ERROR @   5927161 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   5927161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```