OTBN Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	116.954us	1	1	100.00
V1	single_binary	otbn_single	3.600m	951.824us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	13.810us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	23.182us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	64.993us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	18.788us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	111.023us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	23.182us	20	20	100.00
		otbn_csr_aliasing	6.000s	18.788us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.033m	2.570ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	27.000s	468.763us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	27.000s	65.655us	10	10	100.00
V2	multi_error	otbn_multi_err	47.000s	573.273us	1	1	100.00
V2	back_to_back	otbn_multi	4.033m	914.265us	10	10	100.00
V2	stress_all	otbn_stress_all	2.017m	931.572us	10	10	100.00
V2	lc_escalation	otbn_escalate	23.000s	242.691us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	28.268us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	60.227us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	18.040us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	21.718us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	136.333us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	136.333us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	13.810us	5	5	100.00
		otbn_csr_rw	6.000s	23.182us	20	20	100.00
		otbn_csr_aliasing	6.000s	18.788us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	42.934us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	13.810us	5	5	100.00
		otbn_csr_rw	6.000s	23.182us	20	20	100.00
		otbn_csr_aliasing	6.000s	18.788us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	42.934us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	14.000s	28.264us	10	10	100.00
		otbn_dmem_err	14.000s	42.125us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	217.870us	5	5	100.00
		otbn_controller_ispr_rdata_err	36.000s	161.268us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	196.146us	5	5	100.00
		otbn_urnd_err	8.000s	25.223us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	31.076us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	24.564us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	31.195us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	8.783m	7.587ms	4	5	80.00
		otbn_tl_intg_err	31.000s	179.530us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	47.000s	513.321us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	116.954us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	14.000s	42.125us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	28.264us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	31.000s	179.530us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	23.000s	242.691us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	28.264us	10	10	100.00
		otbn_dmem_err	14.000s	42.125us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	28.268us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	31.076us	5	5	100.00
		otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	3.600m	951.824us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	28.264us	10	10	100.00
		otbn_dmem_err	14.000s	42.125us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	28.268us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	31.076us	5	5	100.00
		otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	23.000s	242.691us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	28.264us	10	10	100.00
		otbn_dmem_err	14.000s	42.125us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	28.268us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	31.076us	5	5	100.00
		otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	3.600m	951.824us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	17.000s	67.618us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	35.950us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.350m	1.742ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.350m	1.742ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	54.019us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	152.617us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	167.209us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	167.209us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	19.000s	46.230us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	3.600m	951.824us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	3.600m	951.824us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	3.600m	951.824us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	4.033m	914.265us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	3.600m	951.824us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	3.600m	951.824us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	25.000s	195.868us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	3.600m	951.824us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.783m	7.587ms	4	5	80.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	10.967m	2.660ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			579	585	98.97

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.94	99.59	95.27	99.69	93.55	92.79	97.44	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 3 failures:

Test otbn_partial_wipe has 2 failures.

0.otbn_partial_wipe.15529185476896217839068983233889750194719224614170513888013521128495726176337
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 12954005 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  12954005 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  12954005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_partial_wipe.8146949580484951815032678545944005583610288004886423961541373074920595716201
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 8044067 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   8044067 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   8044067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_sec_wipe_err has 1 failures.

6.otbn_sec_wipe_err.89030052421896101744188839537715392395254906397235986208621823401555196606258
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 28212215 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  28212215 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  28212215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

1.otbn_sec_cm.89583005553837859222158496201614965383705182886588048789106122341492102906838
Line 321, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 66552467 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 66552467 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 66552467 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 66552467 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 66552467 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:486) [otbn_single_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.96680711294942200843985495488886729252645617027741852525537071228697756699077
    Line 356, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10035877216 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 10035877216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 34.otbn_escalate.24734629763706370517087790682754408816714332951527020090046405056686587862143
    Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/34.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 69629794 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  69629794 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  69629794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```