OTBN Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	72.577us	1	1	100.00
V1	single_binary	otbn_single	46.000s	171.228us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	45.348us	5	5	100.00
V1	csr_rw	otbn_csr_rw	5.000s	31.411us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	584.905us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	26.832us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	74.577us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	31.411us	20	20	100.00
		otbn_csr_aliasing	6.000s	26.832us	5	5	100.00
V1	mem_walk	otbn_mem_walk	52.000s	2.331ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	928.268us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	37.000s	125.173us	10	10	100.00
V2	multi_error	otbn_multi_err	1.000m	656.790us	1	1	100.00
V2	back_to_back	otbn_multi	11.283m	11.406ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.100m	579.670us	10	10	100.00
V2	lc_escalation	otbn_escalate	19.000s	66.259us	55	60	91.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	27.418us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	31.000s	148.802us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	14.032us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	14.866us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	518.483us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	518.483us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	45.348us	5	5	100.00
		otbn_csr_rw	5.000s	31.411us	20	20	100.00
		otbn_csr_aliasing	6.000s	26.832us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	46.375us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	45.348us	5	5	100.00
		otbn_csr_rw	5.000s	31.411us	20	20	100.00
		otbn_csr_aliasing	6.000s	26.832us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	46.375us	20	20	100.00
V2		TOTAL			241	246	97.97
V2S	mem_integrity	otbn_imem_err	12.000s	38.693us	10	10	100.00
		otbn_dmem_err	13.000s	46.309us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	37.000s	143.272us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	160.111us	5	5	100.00
		otbn_mac_bignum_acc_err	1.133m	293.495us	5	5	100.00
		otbn_urnd_err	6.000s	24.603us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	173.474us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	22.498us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	15.000s	81.488us	7	10	70.00
V2S	tl_intg_err	otbn_sec_cm	7.067m	9.540ms	2	5	40.00
		otbn_tl_intg_err	1.117m	426.138us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	41.000s	236.490us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	72.577us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	46.309us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	38.693us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.117m	426.138us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	19.000s	66.259us	55	60	91.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	38.693us	10	10	100.00
		otbn_dmem_err	13.000s	46.309us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	27.418us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	173.474us	5	5	100.00
		otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	46.000s	171.228us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	38.693us	10	10	100.00
		otbn_dmem_err	13.000s	46.309us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	27.418us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	173.474us	5	5	100.00
		otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	19.000s	66.259us	55	60	91.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	38.693us	10	10	100.00
		otbn_dmem_err	13.000s	46.309us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	27.418us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	173.474us	5	5	100.00
		otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	46.000s	171.228us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	56.314us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	12.116us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.167m	514.859us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.167m	514.859us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	26.000s	2.056ms	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	1.050m	297.363us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	31.936us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	31.936us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	16.000s	30.337us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	46.000s	171.228us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	46.000s	171.228us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	46.000s	171.228us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	11.283m	11.406ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	46.000s	171.228us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	46.000s	171.228us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	17.000s	33.808us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	46.000s	171.228us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.067m	9.540ms	2	5	40.00
V2S		TOTAL			155	163	95.09
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	21.033m	33.227ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			571	585	97.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	16	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	99.61	95.44	99.69	93.47	92.53	97.44	91.49	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

26.otbn_escalate.88701770363044731051415860705009703537547614167437568338601682788232698978521
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 29627015 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  29627015 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  29627015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.otbn_escalate.73362591682115835155584747478678487856789200425484367851210328199715429393491
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/28.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 37730808 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  37730808 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  37730808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 3 failures:

Test otbn_partial_wipe has 2 failures.

0.otbn_partial_wipe.82891480979781479616751610800927229033451236666344256976214367159386495173569
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 7007502 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   7007502 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   7007502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_partial_wipe.114906002368670699170928548852282159618757284988366627490297840368470073964429
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 4213737 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   4213737 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   4213737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_sec_wipe_err has 1 failures.

6.otbn_sec_wipe_err.101912967086214908336619843030748776744099835070441172625015386897882318087447
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 55921857 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  55921857 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  55921857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.25600168191778415265789406195908727455786836796343536506063188015721260953516
Line 268, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 23809857 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 23809857 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 23809857 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 23809857 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 23809857 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.24657245043688187023057707286122386023546517774720466483380493502654205975348
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 2923931 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 2923931 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 2923931 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 2923931 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 2923931 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 2.otbn_rf_base_intg_err.65796284309377067053688657209421770987734790876991605454185814152377613066735
    Line 294, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 2055684837 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0xe8c70018)
  UVM_INFO @ 2055684837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 3.otbn_partial_wipe.92812874911885589288749503192208716251213861629249682347763271150733240979878
    Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 3656375 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3656375 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3656375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:486) [otbn_imem_err_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.95392117758853759651098675387309420211277910081722019535008650469492411495749
    Line 604, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15602148330 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 15602148330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```