OTBN Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	15.000s	57.379us	1	1	100.00
V1	single_binary	otbn_single	1.417m	420.646us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	19.902us	5	5	100.00
V1	csr_rw	otbn_csr_rw	9.000s	86.426us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	93.416us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	18.509us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	36.931us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	9.000s	86.426us	20	20	100.00
		otbn_csr_aliasing	5.000s	18.509us	5	5	100.00
V1	mem_walk	otbn_mem_walk	44.000s	1.436ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	19.000s	1.583ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.033m	180.596us	10	10	100.00
V2	multi_error	otbn_multi_err	53.000s	543.989us	1	1	100.00
V2	back_to_back	otbn_multi	3.367m	9.853ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.900m	2.143ms	10	10	100.00
V2	lc_escalation	otbn_escalate	26.000s	115.679us	55	60	91.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	62.414us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	20.000s	46.552us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	21.990us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	21.636us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	234.886us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	234.886us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	19.902us	5	5	100.00
		otbn_csr_rw	9.000s	86.426us	20	20	100.00
		otbn_csr_aliasing	5.000s	18.509us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	24.839us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	19.902us	5	5	100.00
		otbn_csr_rw	9.000s	86.426us	20	20	100.00
		otbn_csr_aliasing	5.000s	18.509us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	24.839us	20	20	100.00
V2		TOTAL			241	246	97.97
V2S	mem_integrity	otbn_imem_err	14.000s	45.864us	10	10	100.00
		otbn_dmem_err	18.000s	68.450us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	15.000s	127.366us	5	5	100.00
		otbn_controller_ispr_rdata_err	1.317m	276.564us	5	5	100.00
		otbn_mac_bignum_acc_err	4.250m	2.207ms	5	5	100.00
		otbn_urnd_err	9.000s	57.116us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	25.181us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	18.000s	82.236us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	46.099us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	8.583m	7.861ms	2	5	40.00
		otbn_tl_intg_err	29.000s	182.400us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	52.000s	283.665us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	15.000s	57.379us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	18.000s	68.450us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	45.864us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	29.000s	182.400us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	26.000s	115.679us	55	60	91.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	45.864us	10	10	100.00
		otbn_dmem_err	18.000s	68.450us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	62.414us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	25.181us	5	5	100.00
		otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.417m	420.646us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	45.864us	10	10	100.00
		otbn_dmem_err	18.000s	68.450us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	62.414us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	25.181us	5	5	100.00
		otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	26.000s	115.679us	55	60	91.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	45.864us	10	10	100.00
		otbn_dmem_err	18.000s	68.450us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	62.414us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	25.181us	5	5	100.00
		otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.417m	420.646us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	19.000s	107.039us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	20.338us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.067m	1.247ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.067m	1.247ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	43.123us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	319.309us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	121.270us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	121.270us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	29.000s	86.399us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.417m	420.646us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.417m	420.646us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.417m	420.646us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.367m	9.853ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.417m	420.646us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.417m	420.646us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	17.000s	51.997us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.417m	420.646us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.583m	7.861ms	2	5	40.00
V2S		TOTAL			158	163	96.93
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	42.150m	10.245ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			571	585	97.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.91	99.62	95.58	99.70	93.52	92.70	97.44	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_escalate has 3 failures.

1.otbn_escalate.83462021021459260990870334003730560264588682265921889294885904385097890730687
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14137141 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  14137141 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  14137141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.otbn_escalate.25890730714968883968482555481247329731977540627555722481868900426207656047834
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15740405 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  15740405 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  15740405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otbn_stack_addr_integ_chk has 1 failures.

3.otbn_stack_addr_integ_chk.6429941806053172361833661208162325922272501555072635956154756461957281585397
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 38136966 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  38136966 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  38136966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.39415659294230499151616476495660709448327969604933585669493469002222522372769
Line 275, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 26041822 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 26041822 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 26041822 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 26041822 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 26041822 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.27572496946169353423819604352012547027282026976446887056563774637076987000244
Line 322, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 167758476 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 167758476 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 167758476 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 167758476 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 167758476 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 2 failures:

Test otbn_escalate has 2 failures.

27.otbn_escalate.39502368433317451104027017923408028713749773157192262560829019988590193233895
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log

  UVM_ERROR @   5171158 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   5171158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.otbn_escalate.60903810852483843263358895201369834130959088448339721962456764757171305553283
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/43.otbn_escalate/latest/run.log

  UVM_ERROR @   3235619 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   3235619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:486) [otbn_dmem_err_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.73664978244303539223828433152916189353609979549026047729517209339824792857795
    Line 573, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10245144060 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 10245144060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 1.otbn_sec_wipe_err.102468917919237295805746709506728575521663283473209992590532807942546237087326
    Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 34765175 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  34765175 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  34765175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.36784524470601153610607455570560085181148916173244580005263680432435405137669
    Line 473, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 625051841 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 625051841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.38821232802499359021248479465134202504909585304379453381503642791332368091575
    Line 372, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3603132280 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3603132280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:486) [otbn_imem_err_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.63422717900793808516598830153475971492260400367886217326152597522993755788990
    Line 789, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15370504677 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 15370504677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```