OTBN Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	39.936us	1	1	100.00
V1	single_binary	otbn_single	1.850m	491.013us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	20.662us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	24.201us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	142.557us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	15.213us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	48.891us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	24.201us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.213us	5	5	100.00
V1	mem_walk	otbn_mem_walk	47.000s	5.193ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	989.579us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.583m	1.744ms	10	10	100.00
V2	multi_error	otbn_multi_err	53.000s	657.773us	1	1	100.00
V2	back_to_back	otbn_multi	2.700m	1.237ms	10	10	100.00
V2	stress_all	otbn_stress_all	32.567m	8.677ms	10	10	100.00
V2	lc_escalation	otbn_escalate	17.000s	179.695us	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	27.313us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	94.008us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	32.555us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	17.563us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	47.299us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	47.299us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	20.662us	5	5	100.00
		otbn_csr_rw	7.000s	24.201us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.213us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	31.164us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	20.662us	5	5	100.00
		otbn_csr_rw	7.000s	24.201us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.213us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	31.164us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	11.000s	96.764us	10	10	100.00
		otbn_dmem_err	28.000s	192.920us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	27.000s	99.254us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	60.680us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	115.093us	5	5	100.00
		otbn_urnd_err	10.000s	32.287us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	21.738us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	69.317us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	49.639us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	8.083m	2.303ms	3	5	60.00
		otbn_tl_intg_err	26.000s	165.000us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	41.000s	215.075us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	39.936us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	28.000s	192.920us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	96.764us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	26.000s	165.000us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	17.000s	179.695us	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	96.764us	10	10	100.00
		otbn_dmem_err	28.000s	192.920us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	27.313us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	21.738us	5	5	100.00
		otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.850m	491.013us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	96.764us	10	10	100.00
		otbn_dmem_err	28.000s	192.920us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	27.313us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	21.738us	5	5	100.00
		otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	17.000s	179.695us	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	96.764us	10	10	100.00
		otbn_dmem_err	28.000s	192.920us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	27.313us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	21.738us	5	5	100.00
		otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.850m	491.013us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	16.000s	73.517us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	22.299us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	45.000s	177.884us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	45.000s	177.884us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	30.778us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	16.000s	104.275us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	117.757us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	117.757us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	17.000s	69.869us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.850m	491.013us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.850m	491.013us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.850m	491.013us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.700m	1.237ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.850m	491.013us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.850m	491.013us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	181.655us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.850m	491.013us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.083m	2.303ms	3	5	60.00
V2S		TOTAL			158	163	96.93
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	26.933m	8.156ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			576	585	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.97	99.62	95.58	99.70	93.44	92.86	100.00	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 3 failures:

Test otbn_partial_wipe has 2 failures.

0.otbn_partial_wipe.2831736769497413301350837293352154082386482909971217179078898413601592479448
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 14206811 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  14206811 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  14206811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.otbn_partial_wipe.21193410819640412926536404781110490267028100871158284412746002269355899293195
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 6975393 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   6975393 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   6975393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_sec_wipe_err has 1 failures.

1.otbn_sec_wipe_err.48853508177022999486071190655762606625643080565330091255371970736696868293674
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 20256974 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  20256974 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  20256974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

2.otbn_sec_cm.26428627367457743519689300101090569155872438560561947306074827348277552092108
Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 75297154 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 75297154 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 75297154 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 75297154 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 75297154 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

4.otbn_sec_cm.83796484849960862298931782906732400457431126272696170055379224642508067390620
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 3148401 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 3148401 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 3148401 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 3148401 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 3148401 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 4.otbn_stress_all_with_rand_reset.41873321205777871026818156421619117813010837988617222456130651855977651321110
    Line 746, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11689603031 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11689603031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otbn_stress_all_with_rand_reset.113084582553399857151504159678705242170845610865766802095105649043962930795218
    Line 527, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8156238201 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8156238201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_zero_state_err_urnd has 1 failures.
  - 0.otbn_zero_state_err_urnd.63843898630349335029901791626109224980948878633679788238425289325458424120149
    Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8604501 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   8604501 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   8604501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.35531585799398430104150170433873511449786956959910830551203358588661227998998
    Line 638, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1795466792 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1795466792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```