OTBN Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	41.315us	1	1	100.00
V1	single_binary	otbn_single	31.000s	131.972us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	9.000s	21.080us	5	5	100.00
V1	csr_rw	otbn_csr_rw	12.000s	13.441us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	1.287ms	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	9.000s	33.612us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	15.000s	61.810us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	12.000s	13.441us	20	20	100.00
		otbn_csr_aliasing	9.000s	33.612us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.033m	10.547ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	130.285us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.183m	346.094us	10	10	100.00
V2	multi_error	otbn_multi_err	53.000s	680.603us	1	1	100.00
V2	back_to_back	otbn_multi	1.650m	267.332us	10	10	100.00
V2	stress_all	otbn_stress_all	17.017m	4.727ms	10	10	100.00
V2	lc_escalation	otbn_escalate	30.000s	94.105us	56	60	93.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	16.993us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	20.000s	49.391us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	19.575us	50	50	100.00
V2	intr_test	otbn_intr_test	15.000s	38.718us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	186.432us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	186.432us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	9.000s	21.080us	5	5	100.00
		otbn_csr_rw	12.000s	13.441us	20	20	100.00
		otbn_csr_aliasing	9.000s	33.612us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	43.444us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	9.000s	21.080us	5	5	100.00
		otbn_csr_rw	12.000s	13.441us	20	20	100.00
		otbn_csr_aliasing	9.000s	33.612us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	43.444us	20	20	100.00
V2		TOTAL			241	246	97.97
V2S	mem_integrity	otbn_imem_err	11.000s	23.445us	10	10	100.00
		otbn_dmem_err	16.000s	29.341us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	217.680us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	27.296us	5	5	100.00
		otbn_mac_bignum_acc_err	17.000s	540.617us	5	5	100.00
		otbn_urnd_err	17.000s	82.701us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	37.077us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	29.258us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	53.883us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	6.733m	1.980ms	3	5	60.00
		otbn_tl_intg_err	36.000s	214.112us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	58.000s	341.812us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	41.315us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	29.341us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	23.445us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	36.000s	214.112us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	30.000s	94.105us	56	60	93.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	23.445us	10	10	100.00
		otbn_dmem_err	16.000s	29.341us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	16.993us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	37.077us	5	5	100.00
		otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	31.000s	131.972us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	23.445us	10	10	100.00
		otbn_dmem_err	16.000s	29.341us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	16.993us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	37.077us	5	5	100.00
		otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	30.000s	94.105us	56	60	93.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	23.445us	10	10	100.00
		otbn_dmem_err	16.000s	29.341us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	16.993us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	37.077us	5	5	100.00
		otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	31.000s	131.972us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	13.000s	94.003us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	67.174us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	30.000s	172.875us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	30.000s	172.875us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	186.178us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	213.337us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	19.000s	71.704us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	19.000s	71.704us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	34.924us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	31.000s	131.972us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	31.000s	131.972us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	31.000s	131.972us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.650m	267.332us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	31.000s	131.972us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	31.000s	131.972us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	13.000s	36.929us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	31.000s	131.972us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.733m	1.980ms	3	5	60.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	23.517m	43.415ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			573	585	97.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.92	99.61	95.53	99.70	93.52	92.90	100.00	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_zero_state_err_urnd has 1 failures.

1.otbn_zero_state_err_urnd.74713894227004496018996306215648663162932816304447145896159654189407566189905
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13201361 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  13201361 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  13201361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 4 failures.

8.otbn_escalate.15778840828415915668819666627504554414895295573061038461382320563478366860163
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 43506300 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  43506300 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  43506300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.otbn_escalate.32770506093544369571785919863493462827213011403947704624591262801308330765285
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 46919334 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  46919334 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  46919334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.45571150069809822308682988495642262729083715365766795128602954833319945448584
Line 335, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 176919803 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 176919803 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 176919803 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 176919803 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 176919803 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

4.otbn_sec_cm.10546347472698251893477129995781048249376589920057079344585780417771574388392
Line 365, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 94574343 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 94574343 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 94574343 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 94574343 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 94574343 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 2.otbn_stress_all_with_rand_reset.55095163769417649530802490937709817567222442757673687445494903127263427036777
    Line 743, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3938962910 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 3938962910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otbn_stress_all_with_rand_reset.23481735578735595386122008634725829261643848610762655619255140939758656987749
    Line 322, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   2925238 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @   2925238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:

Test otbn_partial_wipe has 2 failures.

5.otbn_partial_wipe.11341450342787381415707333180703202505394996126903291035547117012535203713050
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 3353023 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   3353023 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   3353023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_partial_wipe.12957339649309263063775764611978622788250312378435425589550106752789134878254
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 11995029 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  11995029 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  11995029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.103241382700293992663647048595023834124472731436972375079926071601655784091623
    Line 703, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43415227002 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 43415227002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```