OTBN Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	41.000s	179.087us	1	1	100.00
V1	single_binary	otbn_single	3.250m	820.309us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	22.686us	5	5	100.00
V1	csr_rw	otbn_csr_rw	8.000s	26.676us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	54.361us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	26.106us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	58.322us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	8.000s	26.676us	20	20	100.00
		otbn_csr_aliasing	8.000s	26.106us	5	5	100.00
V1	mem_walk	otbn_mem_walk	50.000s	1.193ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	430.198us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	36.000s	130.574us	10	10	100.00
V2	multi_error	otbn_multi_err	1.100m	269.977us	1	1	100.00
V2	back_to_back	otbn_multi	23.717m	7.381ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.783m	461.377us	10	10	100.00
V2	lc_escalation	otbn_escalate	15.000s	250.628us	56	60	93.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	18.506us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	26.000s	84.299us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	21.917us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	20.129us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	42.145us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	42.145us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	22.686us	5	5	100.00
		otbn_csr_rw	8.000s	26.676us	20	20	100.00
		otbn_csr_aliasing	8.000s	26.106us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	114.059us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	22.686us	5	5	100.00
		otbn_csr_rw	8.000s	26.676us	20	20	100.00
		otbn_csr_aliasing	8.000s	26.106us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	114.059us	20	20	100.00
V2		TOTAL			242	246	98.37
V2S	mem_integrity	otbn_imem_err	14.000s	28.493us	10	10	100.00
		otbn_dmem_err	16.000s	63.268us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	1.567m	399.577us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	28.872us	5	5	100.00
		otbn_mac_bignum_acc_err	1.633m	4.293ms	5	5	100.00
		otbn_urnd_err	8.000s	17.133us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	54.877us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	133.797us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	37.231us	7	10	70.00
V2S	tl_intg_err	otbn_sec_cm	3.317m	983.721us	3	5	60.00
		otbn_tl_intg_err	57.000s	404.734us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	39.000s	236.384us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	41.000s	179.087us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	63.268us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	28.493us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	57.000s	404.734us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	15.000s	250.628us	56	60	93.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	28.493us	10	10	100.00
		otbn_dmem_err	16.000s	63.268us	15	15	100.00
		otbn_zero_state_err_urnd	7.000s	18.506us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	54.877us	5	5	100.00
		otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	3.250m	820.309us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	28.493us	10	10	100.00
		otbn_dmem_err	16.000s	63.268us	15	15	100.00
		otbn_zero_state_err_urnd	7.000s	18.506us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	54.877us	5	5	100.00
		otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	15.000s	250.628us	56	60	93.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	28.493us	10	10	100.00
		otbn_dmem_err	16.000s	63.268us	15	15	100.00
		otbn_zero_state_err_urnd	7.000s	18.506us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	54.877us	5	5	100.00
		otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	3.250m	820.309us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	173.186us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	28.431us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	34.000s	115.047us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	34.000s	115.047us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	17.000s	43.545us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	2.417m	1.844ms	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	37.302us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	37.302us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	20.544us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	3.250m	820.309us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	3.250m	820.309us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	3.250m	820.309us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	23.717m	7.381ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	3.250m	820.309us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	3.250m	820.309us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	20.000s	59.312us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	3.250m	820.309us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.317m	983.721us	3	5	60.00
V2S		TOTAL			157	163	96.32
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.367m	1.309ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			567	585	96.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.59	95.22	99.69	93.44	92.47	97.44	91.14	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:849) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test otbn_stress_all_with_rand_reset has 5 failures.
  - 3.otbn_stress_all_with_rand_reset.1747837449912412452099243162234562371416975160198974830897810561547541523139
    Line 327, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1600672686 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1600672686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otbn_stress_all_with_rand_reset.962077825857204811062757770464453207200359117330609188522432473788170759938
    Line 358, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2063109670 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2063109670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

0.otbn_escalate.43224716604108994711294234272351498679452163797637062062480424178723357029308
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 10039031 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  10039031 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  10039031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_escalate.100066968209451828609222561044258669687639147589313441059599681184947436924468
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 61732136 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  61732136 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  61732136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.24277770537023585481433548336366701680195679981919461782857185257709236561373
    Line 398, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 891657489 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 891657489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otbn_stress_all_with_rand_reset.108904084434285266175428337395041034821017368366838418807400150616600514562250
    Line 676, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1308562890 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1308562890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

0.otbn_sec_cm.18548365858499386754144218631341554504806797154989275248880484001325763890658
Line 294, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 156928213 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 156928213 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 156928213 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 156928213 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 156928213 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.6217175302358586529614868422355405002355638358369932633668681995982240528123
Line 294, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 149606046 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 149606046 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 149606046 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 149606046 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 149606046 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:

Test otbn_partial_wipe has 2 failures.

6.otbn_partial_wipe.91952185865241444714353187972909035801209964383330961525097966651104874391987
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 6987340 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   6987340 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   6987340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_partial_wipe.104467233983430000253471463841041084488836673114784460522336404294071718279826
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 11143366 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  11143366 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  11143366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:849) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.64785069402912410103583345017187371575990213462380485757986251100653622653623
    Line 333, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 206406142 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 206406142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 4.otbn_partial_wipe.38319176240348701636508192785920268427835683245658705314508762032352573644895
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 35980388 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  35980388 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  35980388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:24) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 6.otbn_ctrl_redun.35275045072737666706599783135702442743931625130411314273129205993137934901128
    Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @  32276179 ps: (otbn_ctrl_redun_vseq.sv:24) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  32276179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```