OTBN Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	26.000s	113.710us	1	1	100.00
V1	single_binary	otbn_single	1.000m	461.480us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	15.686us	5	5	100.00
V1	csr_rw	otbn_csr_rw	8.000s	22.159us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	305.954us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	29.993us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	84.414us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	8.000s	22.159us	20	20	100.00
		otbn_csr_aliasing	5.000s	29.993us	5	5	100.00
V1	mem_walk	otbn_mem_walk	57.000s	7.410ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	2.019ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.050m	262.886us	10	10	100.00
V2	multi_error	otbn_multi_err	45.000s	680.287us	1	1	100.00
V2	back_to_back	otbn_multi	2.350m	1.980ms	10	10	100.00
V2	stress_all	otbn_stress_all	3.583m	1.452ms	10	10	100.00
V2	lc_escalation	otbn_escalate	24.000s	191.780us	55	60	91.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	81.111us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	54.000s	188.182us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	18.685us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	14.918us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	489.716us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	489.716us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	15.686us	5	5	100.00
		otbn_csr_rw	8.000s	22.159us	20	20	100.00
		otbn_csr_aliasing	5.000s	29.993us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	33.008us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	15.686us	5	5	100.00
		otbn_csr_rw	8.000s	22.159us	20	20	100.00
		otbn_csr_aliasing	5.000s	29.993us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	33.008us	20	20	100.00
V2		TOTAL			241	246	97.97
V2S	mem_integrity	otbn_imem_err	12.000s	29.581us	10	10	100.00
		otbn_dmem_err	13.000s	27.248us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	79.602us	5	5	100.00
		otbn_controller_ispr_rdata_err	18.000s	271.456us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	62.637us	5	5	100.00
		otbn_urnd_err	7.000s	28.786us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	17.844us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	27.113us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	31.683us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	40.000s	204.758us	0	5	0.00
		otbn_tl_intg_err	37.000s	406.835us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	49.000s	194.095us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	prim_count_check	otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	26.000s	113.710us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	27.248us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	29.581us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	37.000s	406.835us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	24.000s	191.780us	55	60	91.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	29.581us	10	10	100.00
		otbn_dmem_err	13.000s	27.248us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	81.111us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	17.844us	5	5	100.00
		otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.000m	461.480us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	29.581us	10	10	100.00
		otbn_dmem_err	13.000s	27.248us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	81.111us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	17.844us	5	5	100.00
		otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	24.000s	191.780us	55	60	91.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	29.581us	10	10	100.00
		otbn_dmem_err	13.000s	27.248us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	81.111us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	17.844us	5	5	100.00
		otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.000m	461.480us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	50.093us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	28.404us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.000m	433.676us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.000m	433.676us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	18.000s	139.011us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	22.000s	123.399us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	15.000s	46.895us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	15.000s	46.895us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	31.141us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.000m	461.480us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.000m	461.480us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.000m	461.480us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.350m	1.980ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.000m	461.480us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.000m	461.480us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	36.321us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.000m	461.480us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	40.000s	204.758us	0	5	0.00
V2S		TOTAL			157	163	96.32
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	5.983m	5.420ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			566	585	96.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.82	99.54	94.47	99.65	93.26	92.26	97.44	95.22	95.80

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 5 failures:

Test otbn_sec_cm has 5 failures.

0.otbn_sec_cm.62192641707213035652840956947919660257148608463524519747345686541141973512123
Line 305, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 50485961 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 50485961 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 50485961 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 50485961 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 50485961 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.33341883993018056053097280169168054254694931739806974885861258655711527355258
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 204757591 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 204757591 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 204757591 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 204757591 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 204757591 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 0.otbn_stress_all_with_rand_reset.62628335211871071923318887521488180208388659944856412813856372982466299921421
    Line 459, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1075360110 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1075360110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.otbn_stress_all_with_rand_reset.109064613941338801146309506298977170946272187172594365184565078222220235106327
    Line 710, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 951861031 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 951861031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 1.otbn_stress_all_with_rand_reset.487972092942246906262404181685421829820499346390764879432403555331697818511
    Line 574, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 752320567 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 752320567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stress_all_with_rand_reset.2430808688458529816551863358835627308309730706080060784959290585682899473756
    Line 373, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 207084800 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 207084800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

2.otbn_escalate.103179352569118730581030066846420436265310719735442714428218786476381179596372
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 117084280 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 117084280 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 117084280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.otbn_escalate.78103162663303406418989007900606467279846257656171243268484638909974702810312
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 36258360 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  36258360 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  36258360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 2 failures:

Test otbn_escalate has 2 failures.

39.otbn_escalate.42110331101520532684750067347600303930048709857246146521427416893588192265255
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log

  UVM_ERROR @  27471009 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @  27471009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.otbn_escalate.22455604910578965655234362080350113734373732717726307950243747137974382654440
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/40.otbn_escalate/latest/run.log

  UVM_ERROR @   2698715 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   2698715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 3.otbn_partial_wipe.51262656336013081833298727603911786615292910663893024113099465996660760346365
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 12200288 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  12200288 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  12200288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.64244711999189507085574941814354611005778472958334472354381862914647879846971
    Line 540, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 862104726 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 862104726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.84012088956707420531671858946547149514436023213981512455266560031834141717915
    Line 585, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1168896268 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1168896268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```