OTBN Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: `584c3d46af`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	21.000s	147.082us	1	1	100.00
V1	single_binary	otbn_single	2.350m	1.960ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	138.424us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	15.003us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	166.086us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	10.000s	32.616us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	17.000s	38.566us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	15.003us	20	20	100.00
		otbn_csr_aliasing	10.000s	32.616us	5	5	100.00
V1	mem_walk	otbn_mem_walk	55.000s	1.775ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	909.310us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	54.000s	279.428us	10	10	100.00
V2	multi_error	otbn_multi_err	1.083m	151.050us	1	1	100.00
V2	back_to_back	otbn_multi	23.317m	11.246ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.217m	2.682ms	10	10	100.00
V2	lc_escalation	otbn_escalate	23.000s	164.299us	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	21.845us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	20.000s	50.388us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	29.610us	50	50	100.00
V2	intr_test	otbn_intr_test	11.000s	15.492us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	13.000s	39.606us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	13.000s	39.606us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	138.424us	5	5	100.00
		otbn_csr_rw	10.000s	15.003us	20	20	100.00
		otbn_csr_aliasing	10.000s	32.616us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	34.506us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	138.424us	5	5	100.00
		otbn_csr_rw	10.000s	15.003us	20	20	100.00
		otbn_csr_aliasing	10.000s	32.616us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	34.506us	20	20	100.00
V2		TOTAL			242	246	98.37
V2S	mem_integrity	otbn_imem_err	14.000s	174.766us	10	10	100.00
		otbn_dmem_err	12.000s	24.513us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	773.520us	5	5	100.00
		otbn_controller_ispr_rdata_err	2.600m	622.572us	5	5	100.00
		otbn_mac_bignum_acc_err	16.000s	83.983us	5	5	100.00
		otbn_urnd_err	11.000s	70.047us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	16.031us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	26.077us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	27.166us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	12.633m	3.982ms	3	5	60.00
		otbn_tl_intg_err	49.000s	359.934us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	38.000s	222.775us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	21.000s	147.082us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	24.513us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	174.766us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	49.000s	359.934us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	23.000s	164.299us	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	174.766us	10	10	100.00
		otbn_dmem_err	12.000s	24.513us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	21.845us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	16.031us	5	5	100.00
		otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.350m	1.960ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	174.766us	10	10	100.00
		otbn_dmem_err	12.000s	24.513us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	21.845us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	16.031us	5	5	100.00
		otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	23.000s	164.299us	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	174.766us	10	10	100.00
		otbn_dmem_err	12.000s	24.513us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	21.845us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	16.031us	5	5	100.00
		otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.350m	1.960ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	22.559us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	179.400us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	47.000s	381.401us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	47.000s	381.401us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	31.113us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	17.000s	43.667us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	40.956us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	40.956us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	31.000s	107.067us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.350m	1.960ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.350m	1.960ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.350m	1.960ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	23.317m	11.246ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.350m	1.960ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.350m	1.960ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	27.743us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.350m	1.960ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	12.633m	3.982ms	3	5	60.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	6.033m	2.480ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			573	585	97.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.98	99.61	95.49	99.70	93.49	93.12	100.00	98.72	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_escalate has 2 failures.

1.otbn_escalate.7878609219065929971090695002133166424372752221940828484111385780584034787434
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19708549 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19708549 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  19708549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.otbn_escalate.36806084405829052067920965574377762190247686511352701461939590988352638516598
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 279228117 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 279228117 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 279228117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_zero_state_err_urnd has 1 failures.

4.otbn_zero_state_err_urnd.46730300491459165215529116402047825159196940650140889192218951418786438780079
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32867269 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  32867269 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  32867269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_ctrl_redun has 1 failures.

9.otbn_ctrl_redun.94444912500276888093250301432705944844342171664050108853997924425588650304360
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 4206951 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   4206951 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   4206951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 1.otbn_stress_all_with_rand_reset.94379545982989329381656113006369483576885375413436140303649087819027695301501
    Line 527, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2155634297 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2155634297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.otbn_stress_all_with_rand_reset.73072776905093423240757728871624934569439356950316034798216219012748722687415
    Line 575, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2479571158 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2479571158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.21619046718662455538986013721171927468043236278736468821127470498625571890179
Line 278, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 45344287 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 45344287 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 45344287 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 45344287 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 45344287 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

4.otbn_sec_cm.11590852076582477838469071374804305841473415249621398449973867323413281262669
Line 313, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 219512001 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 219512001 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 219512001 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 219512001 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 219512001 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.91273240811814143728290280333497256679505310490121003837136175639408921322180
    Line 516, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1224673793 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1224673793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.5455563087455364127311996210440537391452719908400102940724406800367500493229
    Line 329, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 121966532 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 121966532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.110235584939635199737177844907022466736742719556412096361364278404480218749982
    Line 422, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 294183767 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 294183767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 38.otbn_escalate.59327155568749574956376053370333781881300456054240432468185199460595873556752
    Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/38.otbn_escalate/latest/run.log
```
  UVM_ERROR @   6098965 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   6098965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```