OTBN Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	145.062us	1	1	100.00
V1	single_binary	otbn_single	1.000m	293.495us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	13.499us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	13.760us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	39.073us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	15.000s	100.008us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	19.000s	198.551us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	13.760us	20	20	100.00
		otbn_csr_aliasing	15.000s	100.008us	5	5	100.00
V1	mem_walk	otbn_mem_walk	56.000s	4.933ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	29.000s	1.793ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	48.000s	244.489us	10	10	100.00
V2	multi_error	otbn_multi_err	53.000s	189.840us	1	1	100.00
V2	back_to_back	otbn_multi	3.017m	719.026us	10	10	100.00
V2	stress_all	otbn_stress_all	1.500m	562.763us	10	10	100.00
V2	lc_escalation	otbn_escalate	34.000s	129.953us	55	60	91.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	13.000s	51.463us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	23.000s	88.051us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	17.073us	50	50	100.00
V2	intr_test	otbn_intr_test	19.000s	11.564us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	307.802us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	307.802us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	13.499us	5	5	100.00
		otbn_csr_rw	10.000s	13.760us	20	20	100.00
		otbn_csr_aliasing	15.000s	100.008us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	43.340us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	13.499us	5	5	100.00
		otbn_csr_rw	10.000s	13.760us	20	20	100.00
		otbn_csr_aliasing	15.000s	100.008us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	43.340us	20	20	100.00
V2		TOTAL			241	246	97.97
V2S	mem_integrity	otbn_imem_err	12.000s	48.234us	10	10	100.00
		otbn_dmem_err	12.000s	33.451us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	52.000s	331.447us	5	5	100.00
		otbn_controller_ispr_rdata_err	8.000s	104.417us	5	5	100.00
		otbn_mac_bignum_acc_err	3.233m	1.015ms	5	5	100.00
		otbn_urnd_err	15.000s	37.618us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	21.305us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	23.384us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	26.474us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	6.500m	1.885ms	4	5	80.00
		otbn_tl_intg_err	51.000s	336.206us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	37.000s	234.343us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	145.062us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	33.451us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	48.234us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	51.000s	336.206us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	34.000s	129.953us	55	60	91.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	48.234us	10	10	100.00
		otbn_dmem_err	12.000s	33.451us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	51.463us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	21.305us	5	5	100.00
		otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.000m	293.495us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	48.234us	10	10	100.00
		otbn_dmem_err	12.000s	33.451us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	51.463us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	21.305us	5	5	100.00
		otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	34.000s	129.953us	55	60	91.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	48.234us	10	10	100.00
		otbn_dmem_err	12.000s	33.451us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	51.463us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	21.305us	5	5	100.00
		otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.000m	293.495us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	86.195us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	38.541us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.800m	449.191us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.800m	449.191us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	31.585us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	114.184us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	168.667us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	168.667us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	59.694us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.000m	293.495us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.000m	293.495us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.000m	293.495us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.017m	719.026us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.000m	293.495us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.000m	293.495us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	21.956us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.000m	293.495us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.500m	1.885ms	4	5	80.00
V2S		TOTAL			161	163	98.77
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	5.667m	22.697ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			573	585	97.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.89	99.61	95.44	99.70	93.47	92.64	100.00	90.44	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

14.otbn_escalate.41365239298196068243671075404809440792606039007782317878075482251210202137652
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 96620678 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  96620678 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  96620678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.otbn_escalate.110056460112795170314892833469565003120915932125384734030439406275419164738834
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 60942122 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  60942122 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  60942122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 0.otbn_stress_all_with_rand_reset.82444815477904702335184675350338478549794039951704635840622195540505593998410
    Line 599, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1214491426 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1214491426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.otbn_stress_all_with_rand_reset.61951306287950476494177708321902893957511627991803451237518295462826418790146
    Line 384, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 548277793 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 548277793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 0.otbn_partial_wipe.70642868818308045029033001828175395753725986966353687264856017406448243676500
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 14186130 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  14186130 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  14186130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.46824650265192486358465537859757186815333438095603402233237987042595419680005
    Line 440, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1184949523 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1184949523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

3.otbn_sec_cm.104967373915069907162830415339928877358109843385347921183801984272011169829989
Line 313, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 125089715 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 125089715 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 125089715 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 125089715 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 125089715 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.25442372974424097403308492319245475823762129927940134592520633849846762925510
    Line 352, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3418680633 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3418680633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 57.otbn_escalate.61068983066219140503750148619246905776104333146419550880670581420257922468501
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/57.otbn_escalate/latest/run.log
```
  UVM_FATAL @ 412989197 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @ 412989197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```