OTBN Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	139.140us	1	1	100.00
V1	single_binary	otbn_single	24.000s	64.516us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	16.393us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	19.260us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	908.376us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	18.682us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	59.531us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	19.260us	20	20	100.00
		otbn_csr_aliasing	6.000s	18.682us	5	5	100.00
V1	mem_walk	otbn_mem_walk	58.000s	7.420ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	251.101us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	46.000s	91.888us	10	10	100.00
V2	multi_error	otbn_multi_err	1.183m	288.986us	1	1	100.00
V2	back_to_back	otbn_multi	2.417m	1.625ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.217m	1.934ms	10	10	100.00
V2	lc_escalation	otbn_escalate	20.000s	83.321us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	30.928us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	61.487us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	34.140us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	17.838us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	646.926us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	646.926us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	16.393us	5	5	100.00
		otbn_csr_rw	6.000s	19.260us	20	20	100.00
		otbn_csr_aliasing	6.000s	18.682us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	43.499us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	16.393us	5	5	100.00
		otbn_csr_rw	6.000s	19.260us	20	20	100.00
		otbn_csr_aliasing	6.000s	18.682us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	43.499us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	14.000s	31.799us	10	10	100.00
		otbn_dmem_err	12.000s	31.799us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	64.828us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	37.891us	5	5	100.00
		otbn_mac_bignum_acc_err	10.000s	258.997us	5	5	100.00
		otbn_urnd_err	9.000s	21.498us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	33.625us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	24.510us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	16.000s	69.833us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	3.667m	3.679ms	2	5	40.00
		otbn_tl_intg_err	49.000s	290.979us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.133m	391.011us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	139.140us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	31.799us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	31.799us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	49.000s	290.979us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	20.000s	83.321us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	31.799us	10	10	100.00
		otbn_dmem_err	12.000s	31.799us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	30.928us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	33.625us	5	5	100.00
		otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	24.000s	64.516us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	31.799us	10	10	100.00
		otbn_dmem_err	12.000s	31.799us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	30.928us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	33.625us	5	5	100.00
		otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	20.000s	83.321us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	31.799us	10	10	100.00
		otbn_dmem_err	12.000s	31.799us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	30.928us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	33.625us	5	5	100.00
		otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	24.000s	64.516us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	17.000s	137.068us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	74.005us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.433m	925.061us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.433m	925.061us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	48.130us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	63.674us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	73.496us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	73.496us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	25.000s	89.029us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	24.000s	64.516us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	24.000s	64.516us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	24.000s	64.516us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.417m	1.625ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	24.000s	64.516us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	24.000s	64.516us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	14.000s	114.631us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	24.000s	64.516us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.667m	3.679ms	2	5	40.00
V2S		TOTAL			157	163	96.32
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	5.983m	865.289us	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			572	585	97.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	16	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.97	99.62	95.62	99.71	93.64	92.76	100.00	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

1.otbn_sec_cm.80576312920294062555451500348855979494281485081978649637619533903236017855146
Line 308, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 162974684 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 162974684 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 162974684 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 162974684 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 162974684 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

3.otbn_sec_cm.115210100056655486501073965735242408303735401132655298217040313642109609977982
Line 333, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 287992757 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 287992757 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 287992757 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 287992757 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 287992757 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 1.otbn_stress_all_with_rand_reset.24177446820002006738595218997056675612526042044675088190532092459103544600094
    Line 420, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 540867029 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 540867029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.otbn_stress_all_with_rand_reset.52385646935024182729055309400500423068848868826756190348163954484434562119122
    Line 444, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1783355782 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1783355782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

2.otbn_stack_addr_integ_chk.81299746440400269214870865036006040654895304771979585803599035576673270956656
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12840881 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  12840881 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  12840881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

19.otbn_escalate.3369236721649495523607709920074419873301382706299323724687405467122695420301
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22764628 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  22764628 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  22764628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.62013141503515528169899833559140991817552589380658019062535101241961045753306
    Line 375, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 408796947 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 408796947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.15176811622245553196940789369619116034770616392044921204104881520987381223088
    Line 332, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 809662627 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 809662627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.44093304602067855052277393450453517157935086527506756917339126838548574155442
    Line 679, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 865289463 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 865289463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 7.otbn_partial_wipe.4079585671374926578513704159320923570135630443477263414062818099816892063950
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 11475327 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  11475327 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  11475327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 8.otbn_rf_base_intg_err.27712034934560286812898181684726779103419834757439607613137854654758051370499
    Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  29049368 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
  UVM_INFO @  29049368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job otbn-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.20021053913483685877590603952963682229540329731216605464295976377770762189672
    Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:882ba830-d3d7-4365-9604-2666badd53e5
```