OTBN Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	303.088us	1	1	100.00
V1	single_binary	otbn_single	6.950m	1.826ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	14.000s	73.062us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	18.241us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	117.513us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	17.642us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	16.000s	191.553us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	18.241us	20	20	100.00
		otbn_csr_aliasing	5.000s	17.642us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.083m	2.840ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	1.476ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	37.000s	160.832us	9	10	90.00
V2	multi_error	otbn_multi_err	1.033m	695.872us	1	1	100.00
V2	back_to_back	otbn_multi	1.967m	1.754ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.717m	1.342ms	10	10	100.00
V2	lc_escalation	otbn_escalate	49.000s	603.557us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	59.323us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	1.483m	440.030us	10	10	100.00
V2	alert_test	otbn_alert_test	15.000s	39.675us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	13.155us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	51.491us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	51.491us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	14.000s	73.062us	5	5	100.00
		otbn_csr_rw	6.000s	18.241us	20	20	100.00
		otbn_csr_aliasing	5.000s	17.642us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	40.860us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	14.000s	73.062us	5	5	100.00
		otbn_csr_rw	6.000s	18.241us	20	20	100.00
		otbn_csr_aliasing	5.000s	17.642us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	40.860us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	12.000s	36.357us	10	10	100.00
		otbn_dmem_err	13.000s	41.977us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	55.541us	5	5	100.00
		otbn_controller_ispr_rdata_err	14.000s	37.020us	5	5	100.00
		otbn_mac_bignum_acc_err	9.000s	55.146us	5	5	100.00
		otbn_urnd_err	11.000s	52.551us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	28.095us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	17.205us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	26.334us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	7.067m	1.836ms	3	5	60.00
		otbn_tl_intg_err	30.000s	453.046us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	43.000s	248.716us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	303.088us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	41.977us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	36.357us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	30.000s	453.046us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	49.000s	603.557us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	36.357us	10	10	100.00
		otbn_dmem_err	13.000s	41.977us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	59.323us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	28.095us	5	5	100.00
		otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	6.950m	1.826ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	36.357us	10	10	100.00
		otbn_dmem_err	13.000s	41.977us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	59.323us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	28.095us	5	5	100.00
		otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	49.000s	603.557us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	36.357us	10	10	100.00
		otbn_dmem_err	13.000s	41.977us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	59.323us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	28.095us	5	5	100.00
		otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	6.950m	1.826ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	68.850us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	29.567us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.300m	738.396us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.300m	738.396us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	44.335us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	70.475us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	91.809us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	91.809us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	28.396us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	6.950m	1.826ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	6.950m	1.826ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	6.950m	1.826ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.967m	1.754ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	6.950m	1.826ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	6.950m	1.826ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	22.000s	62.067us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	6.950m	1.826ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.067m	1.836ms	3	5	60.00
V2S		TOTAL			161	163	98.77
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	7.333m	3.986ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			577	585	98.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	19	95.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.98	99.62	95.62	99.71	93.55	92.96	100.00	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.18315984575425475158946494613914099365029693223740826380852626797075043943242
Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 88497326 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 88497326 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 88497326 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 88497326 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 88497326 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

4.otbn_sec_cm.83130013215772883333587410753608865852356476085989871273517878238767996356788
Line 348, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 860000008 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 860000008 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 860000008 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 860000008 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 860000008 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.22007385001551639557243644275494447872194133416226125865930099717261512901160
    Line 440, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1819149524 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1819149524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.6869738788915828464475823350822775352100558610960201122408380517659858121180
    Line 332, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 169464180 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 169464180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_reset has 1 failures.
  - 7.otbn_reset.78062153795896578133297373780574675993168680836548798442500308538810647298209
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_reset/latest/run.log
```
  UVM_FATAL @  88298592 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  88298592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.37733859094884846494009491050870231709125373303419038064956494124083496236120
    Line 449, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1023783602 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1023783602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.24714629526096155558497939739053954925579270562289900920527490001059481172817
    Line 326, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 179247964 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 179247964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 20.otbn_escalate.38739520092269222232935378018601518724366952742147420165862259729894288866829
    Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 25330865 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  25330865 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  25330865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```