OTBN Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	15.000s	44.701us	1	1	100.00
V1	single_binary	otbn_single	45.000s	692.793us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	29.326us	5	5	100.00
V1	csr_rw	otbn_csr_rw	9.000s	34.766us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	12.000s	72.967us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	25.477us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	19.000s	38.133us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	9.000s	34.766us	20	20	100.00
		otbn_csr_aliasing	6.000s	25.477us	5	5	100.00
V1	mem_walk	otbn_mem_walk	58.000s	3.633ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	1.715ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	35.000s	138.349us	10	10	100.00
V2	multi_error	otbn_multi_err	58.000s	259.228us	1	1	100.00
V2	back_to_back	otbn_multi	2.033m	1.141ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.317m	310.126us	10	10	100.00
V2	lc_escalation	otbn_escalate	1.850m	456.502us	54	60	90.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	30.824us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	154.198us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	22.183us	50	50	100.00
V2	intr_test	otbn_intr_test	11.000s	22.567us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	61.739us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	61.739us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	29.326us	5	5	100.00
		otbn_csr_rw	9.000s	34.766us	20	20	100.00
		otbn_csr_aliasing	6.000s	25.477us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	17.476us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	29.326us	5	5	100.00
		otbn_csr_rw	9.000s	34.766us	20	20	100.00
		otbn_csr_aliasing	6.000s	25.477us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	17.476us	20	20	100.00
V2		TOTAL			239	246	97.15
V2S	mem_integrity	otbn_imem_err	11.000s	20.411us	10	10	100.00
		otbn_dmem_err	13.000s	70.556us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	1.133m	298.270us	5	5	100.00
		otbn_controller_ispr_rdata_err	19.000s	68.335us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	23.193us	5	5	100.00
		otbn_urnd_err	13.000s	54.366us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	58.271us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	13.000s	38.063us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	108.425us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	6.867m	1.820ms	3	5	60.00
		otbn_tl_intg_err	31.000s	197.798us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.083m	390.229us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	15.000s	44.701us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	70.556us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	20.411us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	31.000s	197.798us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.850m	456.502us	54	60	90.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	20.411us	10	10	100.00
		otbn_dmem_err	13.000s	70.556us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	30.824us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	58.271us	5	5	100.00
		otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	45.000s	692.793us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	20.411us	10	10	100.00
		otbn_dmem_err	13.000s	70.556us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	30.824us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	58.271us	5	5	100.00
		otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.850m	456.502us	54	60	90.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	20.411us	10	10	100.00
		otbn_dmem_err	13.000s	70.556us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	30.824us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	58.271us	5	5	100.00
		otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	45.000s	692.793us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	188.303us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	49.686us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	50.000s	700.952us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	50.000s	700.952us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	43.860us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	19.000s	70.984us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	282.746us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	282.746us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	66.629us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	45.000s	692.793us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	45.000s	692.793us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	45.000s	692.793us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.033m	1.141ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	45.000s	692.793us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	45.000s	692.793us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	20.000s	72.273us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	45.000s	692.793us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.867m	1.820ms	3	5	60.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	5.650m	5.946ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			568	585	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.92	99.61	95.44	99.70	93.58	92.14	100.00	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 7 failures:

Test otbn_zero_state_err_urnd has 1 failures.

1.otbn_zero_state_err_urnd.103100196484603541023067286410156486569458167623851878103402408796185035038802
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 10765584 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  10765584 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  10765584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 6 failures.

6.otbn_escalate.81031321923531020171139873644589264671171127928562933112937578099777243512101
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 33887464 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  33887464 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  33887464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_escalate.93736068295608790762436702283701273876143759160516879124732708922128908608665
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 456501618 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 456501618 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 456501618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 2.otbn_stress_all_with_rand_reset.27482109089650773121723901716787055989155136438859483655536040644593826282945
    Line 774, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5946184790 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5946184790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stress_all_with_rand_reset.6988199824774787148467324394939888068873019227613301164807667561894077187925
    Line 402, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2957342097 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2957342097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.74777406885440158819758419292522074171646975487728486401392050626883816293209
    Line 622, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2624873603 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2624873603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otbn_stress_all_with_rand_reset.101419294119210763831169734239245132712174951837027540693035984364262908871877
    Line 337, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 155455069 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 155455069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

0.otbn_sec_cm.38982630240057185193030169736035235023654006686308716054839115951799107142565
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 72366391 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 72366391 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 72366391 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 72366391 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 72366391 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

2.otbn_sec_cm.47033218160136723338433626934013250278535500700579552821570431085711242801750
Line 276, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 12955032 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 12955032 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 12955032 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 12955032 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 12955032 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.77474206277866776695739047818810911454652686509605822046053864584795563291498
    Line 334, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 121091790 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 121091790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 4.otbn_rf_base_intg_err.102017547598863256255757177026647724666229453021267472754176537956506381072153
    Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  27875736 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
  UVM_INFO @  27875736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 9.otbn_partial_wipe.60496517826309823973775756176423841456000621316039665935879233551648978290006
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 7756644 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   7756644 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   7756644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```