OTBN Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	16.000s	227.875us	1	1	100.00
V1	single_binary	otbn_single	55.000s	792.193us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	39.293us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	104.009us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	67.878us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	46.004us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	161.870us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	104.009us	20	20	100.00
		otbn_csr_aliasing	6.000s	46.004us	5	5	100.00
V1	mem_walk	otbn_mem_walk	55.000s	3.642ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	380.292us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	42.000s	192.628us	10	10	100.00
V2	multi_error	otbn_multi_err	59.000s	330.242us	1	1	100.00
V2	back_to_back	otbn_multi	1.167m	553.222us	10	10	100.00
V2	stress_all	otbn_stress_all	2.367m	1.250ms	10	10	100.00
V2	lc_escalation	otbn_escalate	33.000s	134.459us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	25.924us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	49.000s	265.420us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	34.621us	50	50	100.00
V2	intr_test	otbn_intr_test	11.000s	16.150us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	520.989us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	520.989us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	39.293us	5	5	100.00
		otbn_csr_rw	6.000s	104.009us	20	20	100.00
		otbn_csr_aliasing	6.000s	46.004us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	20.420us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	39.293us	5	5	100.00
		otbn_csr_rw	6.000s	104.009us	20	20	100.00
		otbn_csr_aliasing	6.000s	46.004us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	20.420us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	13.000s	26.857us	10	10	100.00
		otbn_dmem_err	18.000s	28.315us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	67.001us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	546.539us	5	5	100.00
		otbn_mac_bignum_acc_err	28.000s	276.599us	5	5	100.00
		otbn_urnd_err	6.000s	30.933us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	20.702us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	582.752us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	13.000s	72.173us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	12.417m	4.202ms	3	5	60.00
		otbn_tl_intg_err	35.000s	375.925us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	48.000s	273.875us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	16.000s	227.875us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	18.000s	28.315us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	26.857us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	35.000s	375.925us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	33.000s	134.459us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	26.857us	10	10	100.00
		otbn_dmem_err	18.000s	28.315us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	25.924us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	20.702us	5	5	100.00
		otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	55.000s	792.193us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	26.857us	10	10	100.00
		otbn_dmem_err	18.000s	28.315us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	25.924us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	20.702us	5	5	100.00
		otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	33.000s	134.459us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	26.857us	10	10	100.00
		otbn_dmem_err	18.000s	28.315us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	25.924us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	20.702us	5	5	100.00
		otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	55.000s	792.193us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	17.000s	65.824us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	22.696us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.083m	944.424us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.083m	944.424us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	35.312us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	74.647us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	38.000s	135.438us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	38.000s	135.438us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	24.000s	54.314us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	55.000s	792.193us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	55.000s	792.193us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	55.000s	792.193us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.167m	553.222us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	55.000s	792.193us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	55.000s	792.193us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	22.000s	43.129us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	55.000s	792.193us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	12.417m	4.202ms	3	5	60.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	6.967m	11.726ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			576	585	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.97	99.62	95.62	99.71	93.55	92.80	100.00	98.83	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_zero_state_err_urnd has 1 failures.

1.otbn_zero_state_err_urnd.14993059454674890830547228601980451574632063325222799151829059629753910186827
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16985561 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  16985561 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  16985561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

4.otbn_escalate.65838775049127951247497058980655392218869232992063230207202023989814124641036
Line 295, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12882736 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  12882736 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  12882736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

3.otbn_sec_cm.97425697347752234486033838874571896341369313872842165558453803252105730293723
Line 346, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 88867476 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 88867476 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 88867476 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 88867476 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 88867476 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

4.otbn_sec_cm.103042286257225874681884590757372933662967700924212253807069987659576863233145
Line 338, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 137825881 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 137825881 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 137825881 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 137825881 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 137825881 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 5.otbn_stress_all_with_rand_reset.2726455303695410477658529747805141295013025714589867898677296585812245844431
    Line 336, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 168479628 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 168479628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otbn_stress_all_with_rand_reset.60530487523507755272905639223119695047808239726843409828581481118630461260935
    Line 381, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1436630162 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1436630162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_rnd_if.sv,175): Assertion EdgePREFETCHINGToFULL_A has failed (* cycles, starting * PS) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.8938266910218685510623313892882537555727777929680337951871484813034563830031
    Line 377, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_rnd_if.sv,175): (time 91696066 PS) Assertion tb.dut.u_otbn_core.u_otbn_rnd.i_otbn_rnd_if.EdgePREFETCHINGToFULL_A has failed (2 cycles, starting 91685965 PS)
  UVM_ERROR @  91696066 ps: (otbn_rnd_if.sv:175) [ASSERT FAILED] EdgePREFETCHINGToFULL_A
  UVM_INFO @  91696066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 7.otbn_partial_wipe.97479282437017928549379778621478014709467804603086200752144417468830313644389
    Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 6239103 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
  UVM_ERROR @   6239103 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
  UVM_INFO @   6239103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.30761020969555057961120240238434269160822483981980117968732110847462623944014
    Line 509, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1549528784 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1549528784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```