OTBN Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 5.713s 0 1 0.00
V1 single_binary otbn_single 11.767s 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 7.000s 25.461us 5 5 100.00
V1 csr_rw otbn_csr_rw 7.000s 15.473us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 12.000s 104.288us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 20.479us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 13.000s 58.252us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 7.000s 15.473us 20 20 100.00
otbn_csr_aliasing 6.000s 20.479us 5 5 100.00
V1 mem_walk otbn_mem_walk 59.000s 3.641ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 26.000s 441.167us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 11.706s 0 10 0.00
V2 multi_error otbn_multi_err 4.569s 0 1 0.00
V2 back_to_back otbn_multi 6.576s 0 10 0.00
V2 stress_all otbn_stress_all 10.209s 0 10 0.00
V2 lc_escalation otbn_escalate 14.359s 0 60 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 7.252s 0 5 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 14.415s 0 10 0.00
V2 alert_test otbn_alert_test 7.000s 16.253us 50 50 100.00
V2 intr_test otbn_intr_test 8.000s 20.220us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 13.000s 174.924us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 13.000s 174.924us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 7.000s 25.461us 5 5 100.00
otbn_csr_rw 7.000s 15.473us 20 20 100.00
otbn_csr_aliasing 6.000s 20.479us 5 5 100.00
otbn_same_csr_outstanding 9.000s 34.890us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 7.000s 25.461us 5 5 100.00
otbn_csr_rw 7.000s 15.473us 20 20 100.00
otbn_csr_aliasing 6.000s 20.479us 5 5 100.00
otbn_same_csr_outstanding 9.000s 34.890us 20 20 100.00
V2 TOTAL 140 246 56.91
V2S mem_integrity otbn_imem_err 8.260s 0 10 0.00
otbn_dmem_err 12.928s 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 10.516s 0 5 0.00
otbn_controller_ispr_rdata_err 5.627s 0 5 0.00
otbn_mac_bignum_acc_err 6.515s 0 5 0.00
otbn_urnd_err 7.537s 0 2 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 18.594s 0 5 0.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.491s 0 2 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.335s 0 10 0.00
V2S tl_intg_err otbn_sec_cm 10.050m 2.068ms 2 5 40.00
otbn_tl_intg_err 35.000s 143.312us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 1.667m 395.123us 20 20 100.00
V2S prim_fsm_check otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S prim_count_check otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S sec_cm_mem_scramble otbn_smoke 5.713s 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 12.928s 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 8.260s 0 10 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 35.000s 143.312us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 14.359s 0 60 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 8.260s 0 10 0.00
otbn_dmem_err 12.928s 0 15 0.00
otbn_zero_state_err_urnd 7.252s 0 5 0.00
otbn_illegal_mem_acc 18.594s 0 5 0.00
otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S sec_cm_scramble_key_sideload otbn_single 11.767s 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 8.260s 0 10 0.00
otbn_dmem_err 12.928s 0 15 0.00
otbn_zero_state_err_urnd 7.252s 0 5 0.00
otbn_illegal_mem_acc 18.594s 0 5 0.00
otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 14.359s 0 60 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 8.260s 0 10 0.00
otbn_dmem_err 12.928s 0 15 0.00
otbn_zero_state_err_urnd 7.252s 0 5 0.00
otbn_illegal_mem_acc 18.594s 0 5 0.00
otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S sec_cm_data_reg_sw_sca otbn_single 11.767s 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 7.838s 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 10.591s 0 5 0.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 14.497s 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 14.497s 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 10.921s 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 12.967s 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 5.387s 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 5.387s 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 5.187s 0 7 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 11.767s 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 11.767s 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 11.767s 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 6.576s 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 11.767s 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 11.767s 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 6.013s 0 5 0.00
V2S sec_cm_key_sideload otbn_single 11.767s 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 10.050m 2.068ms 2 5 40.00
V2S TOTAL 42 163 25.77
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 11.913s 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 247 585 42.22

Testplan Progress

Items Total Written Passing Progress
V1 9 9 7 77.78
V2 11 11 4 36.36
V2S 20 20 2 10.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
92.18 97.21 64.26 96.45 74.04 48.86 51.28 75.85 96.22

Failure Buckets

Past Results