OTBN Simulation Results

Friday August 23 2024 20:11:09 UTC

GitHub Revision: `33c4b71134`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	15.000s	39.344us	1	1	100.00
V1	single_binary	otbn_single	2.783m	562.035us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	21.726us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	16.539us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	13.000s	890.039us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	136.230us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	40.427us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	16.539us	20	20	100.00
		otbn_csr_aliasing	7.000s	136.230us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.150m	7.456ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	476.946us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.617m	399.751us	10	10	100.00
V2	multi_error	otbn_multi_err	1.033m	321.524us	1	1	100.00
V2	back_to_back	otbn_multi	1.633m	605.469us	10	10	100.00
V2	stress_all	otbn_stress_all	2.350m	366.131us	10	10	100.00
V2	lc_escalation	otbn_escalate	42.000s	266.639us	56	60	93.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	23.962us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	1.367m	253.333us	10	10	100.00
V2	alert_test	otbn_alert_test	12.000s	23.946us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	17.430us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	14.000s	122.639us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	14.000s	122.639us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	21.726us	5	5	100.00
		otbn_csr_rw	7.000s	16.539us	20	20	100.00
		otbn_csr_aliasing	7.000s	136.230us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	31.791us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	21.726us	5	5	100.00
		otbn_csr_rw	7.000s	16.539us	20	20	100.00
		otbn_csr_aliasing	7.000s	136.230us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	31.791us	20	20	100.00
V2		TOTAL			241	246	97.97
V2S	mem_integrity	otbn_imem_err	29.000s	75.259us	10	10	100.00
		otbn_dmem_err	23.000s	311.397us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	59.452us	5	5	100.00
		otbn_controller_ispr_rdata_err	14.000s	34.629us	5	5	100.00
		otbn_mac_bignum_acc_err	15.000s	62.520us	5	5	100.00
		otbn_urnd_err	11.000s	12.799us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	12.000s	24.061us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	75.097us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	17.153us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	7.083m	21.755ms	1	5	20.00
		otbn_tl_intg_err	1.167m	383.884us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	53.000s	196.182us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	prim_count_check	otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	sec_cm_mem_scramble	otbn_smoke	15.000s	39.344us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	23.000s	311.397us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	29.000s	75.259us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.167m	383.884us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	42.000s	266.639us	56	60	93.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	29.000s	75.259us	10	10	100.00
		otbn_dmem_err	23.000s	311.397us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	23.962us	4	5	80.00
		otbn_illegal_mem_acc	12.000s	24.061us	5	5	100.00
		otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.783m	562.035us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	29.000s	75.259us	10	10	100.00
		otbn_dmem_err	23.000s	311.397us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	23.962us	4	5	80.00
		otbn_illegal_mem_acc	12.000s	24.061us	5	5	100.00
		otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	42.000s	266.639us	56	60	93.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	29.000s	75.259us	10	10	100.00
		otbn_dmem_err	23.000s	311.397us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	23.962us	4	5	80.00
		otbn_illegal_mem_acc	12.000s	24.061us	5	5	100.00
		otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.783m	562.035us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	162.306us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	63.309us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.017m	646.857us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.017m	646.857us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	35.086us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	62.087us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	221.666us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	221.666us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	22.744us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.783m	562.035us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.783m	562.035us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.783m	562.035us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.633m	605.469us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.783m	562.035us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.783m	562.035us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	29.000s	58.960us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.783m	562.035us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.083m	21.755ms	1	5	20.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.100m	7.121ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			568	585	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	19	95.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.97	99.61	95.53	99.71	93.58	92.79	100.00	98.60	99.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test otbn_stress_all_with_rand_reset has 6 failures.
  - 0.otbn_stress_all_with_rand_reset.68393579944431309705840916139227216419396389318610522910356005079422012713988
    Line 295, in log /workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1299777339 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1299777339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.otbn_stress_all_with_rand_reset.59585434519013107193881929611442411495041625546490059660356226513594639081254
    Line 620, in log /workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7121397697 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7121397697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 4 failures:

Test otbn_sec_cm has 4 failures.

0.otbn_sec_cm.3860993717137123351039583496511618585787045684711763069906662694450435961092
Line 122, in log /workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 215543301 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 215543301 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 215543301 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 215543301 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 215543301 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.105869047377245746805908251879688086870950162041978106843766995106720865465690
Line 83, in log /workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 46413785 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 46413785 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 46413785 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 46413785 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 46413785 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 2 more failures.

xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_zero_state_err_urnd has 1 failures.

3.otbn_zero_state_err_urnd.31516525402012761458796322557465788327201999923032924182069835065600992446556
Line 94, in log /workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/3.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 11176395 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  11176395 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  11176395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 3 failures.

10.otbn_escalate.3498753780760588917533732784062387191911399283398319289382444311924267761886
Line 98, in log /workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12841663 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  12841663 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  12841663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.otbn_escalate.76870411615619909713754403430469453686400102068700125759072189855816171642497
Line 93, in log /workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/23.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12444388 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  12444388 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  12444388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 3.otbn_stress_all_with_rand_reset.96763765007034887400968037796485052513408713715362379197015706804026193717195
    Line 337, in log /workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 640766685 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 640766685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otbn_stress_all_with_rand_reset.108271245556415529313423104233683724195822504398448693597470115407232848964205
    Line 296, in log /workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2204234918 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2204234918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 24.otbn_escalate.104940769918463813405478861111869626151257116461312924711044934285679704809045
    Line 91, in log /workspaces/lowrisc/opentitan/scratch/master/otbn-sim-xcelium/24.otbn_escalate/latest/run.log
```
  UVM_ERROR @   5116736 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   5116736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```