OTBN Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Simulator: XCELIUM

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	18.000s	195.927us	1	1	100.00
V1	single_binary	otbn_single	31.000s	112.142us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	1.333m	25.505us	5	5	100.00
V1	csr_rw	otbn_csr_rw	1.350m	16.136us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	23.000s	208.098us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	22.000s	18.398us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	1.400m	358.638us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	1.350m	16.136us	20	20	100.00
		otbn_csr_aliasing	22.000s	18.398us	5	5	100.00
V1	mem_walk	otbn_mem_walk	49.000s	1.862ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	830.133us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	3.433m	1.018ms	10	10	100.00
V2	multi_error	otbn_multi_err	1.050m	532.876us	1	1	100.00
V2	back_to_back	otbn_multi	1.283m	1.010ms	10	10	100.00
V2	stress_all	otbn_stress_all	5.100m	2.847ms	10	10	100.00
V2	lc_escalation	otbn_escalate	21.000s	70.943us	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	23.505us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	2.117m	1.228ms	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	26.383us	50	50	100.00
V2	intr_test	otbn_intr_test	1.333m	21.890us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	1.350m	90.692us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	1.350m	90.692us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	1.333m	25.505us	5	5	100.00
		otbn_csr_rw	1.350m	16.136us	20	20	100.00
		otbn_csr_aliasing	22.000s	18.398us	5	5	100.00
		otbn_same_csr_outstanding	1.317m	60.513us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	1.333m	25.505us	5	5	100.00
		otbn_csr_rw	1.350m	16.136us	20	20	100.00
		otbn_csr_aliasing	22.000s	18.398us	5	5	100.00
		otbn_same_csr_outstanding	1.317m	60.513us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	10.000s	24.399us	10	10	100.00
		otbn_dmem_err	12.000s	64.626us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	20.000s	79.406us	5	5	100.00
		otbn_controller_ispr_rdata_err	21.000s	56.214us	5	5	100.00
		otbn_mac_bignum_acc_err	21.000s	128.749us	5	5	100.00
		otbn_urnd_err	9.000s	136.527us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	20.863us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	12.000s	30.455us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	50.284us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	2.867m	948.521us	3	5	60.00
		otbn_tl_intg_err	1.667m	183.975us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	2.000m	225.894us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	18.000s	195.927us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	64.626us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	24.399us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.667m	183.975us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	21.000s	70.943us	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	24.399us	10	10	100.00
		otbn_dmem_err	12.000s	64.626us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	23.505us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	20.863us	5	5	100.00
		otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	31.000s	112.142us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	24.399us	10	10	100.00
		otbn_dmem_err	12.000s	64.626us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	23.505us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	20.863us	5	5	100.00
		otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	21.000s	70.943us	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	24.399us	10	10	100.00
		otbn_dmem_err	12.000s	64.626us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	23.505us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	20.863us	5	5	100.00
		otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	31.000s	112.142us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	47.954us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	50.425us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.550m	1.049ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.550m	1.049ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	17.000s	47.900us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	21.000s	118.227us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	128.342us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	128.342us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	53.825us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	31.000s	112.142us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	31.000s	112.142us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	31.000s	112.142us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.283m	1.010ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	31.000s	112.142us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	31.000s	112.142us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	40.672us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	31.000s	112.142us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	2.867m	948.521us	3	5	60.00
V2S		TOTAL			161	163	98.77
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	5.583m	1.020ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			573	585	97.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	19	95.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	99.60	95.40	99.69	93.44	92.53	97.44	91.60	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test otbn_stress_all_with_rand_reset has 6 failures.
  - 2.otbn_stress_all_with_rand_reset.92947647120335875541020885223165214890333834365590340276195542150161457709417
    Line 252, in log /workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 377350165 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 377350165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stress_all_with_rand_reset.61122781481903459563239347765173138814014862953080830616403227732310727186584
    Line 428, in log /workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2048331019 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2048331019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.74908434507667437376602240899168314093578750204052018029757926644195491204536
Line 133, in log /workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 112317800 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 112317800 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 112317800 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 112317800 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 112317800 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

2.otbn_sec_cm.8312983382059339597989133033813237685656862652785230714521989103534607501378
Line 168, in log /workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 394320681 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 394320681 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 394320681 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 394320681 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 394320681 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_escalate has 2 failures.

36.otbn_escalate.22477802232863579072892413694052242232421878835713024261639489168875863696358
Line 93, in log /workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/36.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 362729630 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 362729630 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 362729630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.otbn_escalate.76900964997340338833881322015569134399409511105357963851119502769608927977316
Line 96, in log /workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/39.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 126645021 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 126645021 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 126645021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.26813625773562082392328573564005875975942273282582884276974338294818715794938
    Line 151, in log /workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1608522594 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1608522594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 51.otbn_escalate.81295015746309524162962048547841405297078778542486975354037969047809748688279
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_08_22/otbn-sim-xcelium/51.otbn_escalate/latest/run.log
```
  UVM_ERROR @  17349722 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @  17349722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```