OTBN Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Simulator: XCELIUM

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	22.000s	44.856us	1	1	100.00
V1	single_binary	otbn_single	1.633m	478.551us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	36.000s	21.335us	5	5	100.00
V1	csr_rw	otbn_csr_rw	34.000s	17.335us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	41.000s	138.466us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	38.000s	51.588us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	47.000s	74.241us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	34.000s	17.335us	20	20	100.00
		otbn_csr_aliasing	38.000s	51.588us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.567m	4.988ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	40.000s	1.840ms	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	1.267m	190.264us	10	10	100.00
V2	multi_error	otbn_multi_err	5.483m	599.020us	1	1	100.00
V2	back_to_back	otbn_multi	2.367m	222.861us	10	10	100.00
V2	stress_all	otbn_stress_all	2.733m	443.217us	10	10	100.00
V2	lc_escalation	otbn_escalate	58.000s	125.752us	54	60	90.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	14.000s	22.796us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	30.000s	184.604us	10	10	100.00
V2	alert_test	otbn_alert_test	13.000s	24.621us	50	50	100.00
V2	intr_test	otbn_intr_test	36.000s	12.891us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	55.000s	73.300us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	55.000s	73.300us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	36.000s	21.335us	5	5	100.00
		otbn_csr_rw	34.000s	17.335us	20	20	100.00
		otbn_csr_aliasing	38.000s	51.588us	5	5	100.00
		otbn_same_csr_outstanding	41.000s	41.383us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	36.000s	21.335us	5	5	100.00
		otbn_csr_rw	34.000s	17.335us	20	20	100.00
		otbn_csr_aliasing	38.000s	51.588us	5	5	100.00
		otbn_same_csr_outstanding	41.000s	41.383us	20	20	100.00
V2		TOTAL			240	246	97.56
V2S	mem_integrity	otbn_imem_err	18.000s	95.318us	10	10	100.00
		otbn_dmem_err	36.000s	82.426us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	17.000s	66.011us	5	5	100.00
		otbn_controller_ispr_rdata_err	17.000s	54.889us	5	5	100.00
		otbn_mac_bignum_acc_err	16.000s	73.009us	5	5	100.00
		otbn_urnd_err	14.000s	46.253us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	57.025us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	16.575us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	14.000s	29.850us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	22.200m	3.957ms	3	5	60.00
		otbn_tl_intg_err	1.567m	334.333us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.867m	255.097us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	22.000s	44.856us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	36.000s	82.426us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	18.000s	95.318us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.567m	334.333us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	58.000s	125.752us	54	60	90.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	18.000s	95.318us	10	10	100.00
		otbn_dmem_err	36.000s	82.426us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	22.796us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	57.025us	5	5	100.00
		otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.633m	478.551us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	18.000s	95.318us	10	10	100.00
		otbn_dmem_err	36.000s	82.426us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	22.796us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	57.025us	5	5	100.00
		otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	58.000s	125.752us	54	60	90.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	18.000s	95.318us	10	10	100.00
		otbn_dmem_err	36.000s	82.426us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	22.796us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	57.025us	5	5	100.00
		otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.633m	478.551us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	25.000s	141.857us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	16.000s	20.530us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.483m	226.017us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.483m	226.017us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	20.000s	35.909us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	21.000s	65.164us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	82.064us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	82.064us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	21.737us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.633m	478.551us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.633m	478.551us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.633m	478.551us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.367m	222.861us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.633m	478.551us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.633m	478.551us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	26.000s	147.441us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.633m	478.551us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	22.200m	3.957ms	3	5	60.00
V2S		TOTAL			161	163	98.77
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	13.433m	4.888ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			570	585	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	10	90.91
V2S	20	20	19	95.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.98	99.61	95.44	99.70	93.49	93.05	100.00	98.83	99.16

Failure Buckets

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

0.otbn_escalate.52319636423375159968206816970391244551775282035880371787737630773612913116080
Line 93, in log /workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15892718 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  15892718 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  15892718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_escalate.9822981792836629210769141049449397835372174224357824305784527681054187646865
Line 116, in log /workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 125752159 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 125752159 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 125752159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 2.otbn_stress_all_with_rand_reset.115055621330180444354773813357132964345012506369143937698760316047969964012137
    Line 360, in log /workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3433395337 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3433395337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otbn_stress_all_with_rand_reset.34484807002943597759995705240449062121399120073035089823410319701385380259822
    Line 478, in log /workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8648576406 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8648576406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

2.otbn_sec_cm.91686520289378223184186792229754907754386148116470769684614153613267659873301
Line 143, in log /workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 287268552 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 287268552 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 287268552 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 287268552 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 287268552 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

4.otbn_sec_cm.61388611727514709387571421146076450190731951655209060713806803792988304351145
Line 81, in log /workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 17720144 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 17720144 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 17720144 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 17720144 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 17720144 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 4.otbn_stress_all_with_rand_reset.114138797571296017129497367094713332935565496828414833573390976508304306935483
    Line 520, in log /workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4901556420 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 4901556420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otbn_stress_all_with_rand_reset.104632266559978412279159292376766966104674789021937714959411772229128573315165
    Line 166, in log /workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  89752370 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  89752370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.76306182370970552805931789287703271611925483986393400234522871742304542616756
    Line 178, in log /workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1606025641 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1606025641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 37.otbn_escalate.103579831037063068548297738544569046888072630947826096442769790967452566511640
    Line 98, in log /workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/37.otbn_escalate/latest/run.log
```
  UVM_ERROR @   6333450 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   6333450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_single has 1 failures.
  - 57.otbn_single.56988468998767557354181673087306904495005927272491733075106788488022273843560
    Line 88, in log /workspaces/repo/scratch/os_regression_2024_08_24/otbn-sim-xcelium/57.otbn_single/latest/run.log
```
  UVM_FATAL @  31354434 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  31354434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```