OTBN Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: XCELIUM

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	23.000s	482.920us	1	1	100.00
V1	single_binary	otbn_single	7.300m	2.311ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	15.361us	5	5	100.00
V1	csr_rw	otbn_csr_rw	9.000s	16.398us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	13.000s	358.532us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	21.308us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	60.177us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	9.000s	16.398us	20	20	100.00
		otbn_csr_aliasing	8.000s	21.308us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.167m	3.718ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	19.000s	857.321us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.217m	150.005us	10	10	100.00
V2	multi_error	otbn_multi_err	1.300m	476.798us	1	1	100.00
V2	back_to_back	otbn_multi	2.350m	713.624us	10	10	100.00
V2	stress_all	otbn_stress_all	2.550m	356.508us	10	10	100.00
V2	lc_escalation	otbn_escalate	2.900m	1.864ms	55	60	91.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	13.000s	55.443us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	28.000s	69.585us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	24.121us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	20.994us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	15.000s	610.024us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	15.000s	610.024us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	15.361us	5	5	100.00
		otbn_csr_rw	9.000s	16.398us	20	20	100.00
		otbn_csr_aliasing	8.000s	21.308us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	30.893us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	15.361us	5	5	100.00
		otbn_csr_rw	9.000s	16.398us	20	20	100.00
		otbn_csr_aliasing	8.000s	21.308us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	30.893us	20	20	100.00
V2		TOTAL			241	246	97.97
V2S	mem_integrity	otbn_imem_err	17.000s	58.651us	10	10	100.00
		otbn_dmem_err	32.000s	70.623us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	22.000s	177.854us	5	5	100.00
		otbn_controller_ispr_rdata_err	2.200m	323.201us	5	5	100.00
		otbn_mac_bignum_acc_err	18.000s	26.633us	5	5	100.00
		otbn_urnd_err	9.000s	28.601us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	16.000s	61.104us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	13.000s	21.653us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	19.021us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	4.983m	5.353ms	1	5	20.00
		otbn_tl_intg_err	48.000s	220.952us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.217m	273.525us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	prim_count_check	otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	sec_cm_mem_scramble	otbn_smoke	23.000s	482.920us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	32.000s	70.623us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	17.000s	58.651us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	48.000s	220.952us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	2.900m	1.864ms	55	60	91.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	17.000s	58.651us	10	10	100.00
		otbn_dmem_err	32.000s	70.623us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	55.443us	5	5	100.00
		otbn_illegal_mem_acc	16.000s	61.104us	5	5	100.00
		otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	sec_cm_scramble_key_sideload	otbn_single	7.300m	2.311ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	17.000s	58.651us	10	10	100.00
		otbn_dmem_err	32.000s	70.623us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	55.443us	5	5	100.00
		otbn_illegal_mem_acc	16.000s	61.104us	5	5	100.00
		otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	2.900m	1.864ms	55	60	91.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	17.000s	58.651us	10	10	100.00
		otbn_dmem_err	32.000s	70.623us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	55.443us	5	5	100.00
		otbn_illegal_mem_acc	16.000s	61.104us	5	5	100.00
		otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	7.300m	2.311ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	21.000s	54.020us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	18.000s	37.440us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.600m	2.692ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.600m	2.692ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	19.000s	38.216us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	1.100m	136.837us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	26.000s	172.820us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	26.000s	172.820us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	27.726us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	7.300m	2.311ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	7.300m	2.311ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	7.300m	2.311ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.350m	713.624us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	7.300m	2.311ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	7.300m	2.311ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	17.000s	104.443us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	7.300m	2.311ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.983m	5.353ms	1	5	20.00
V2S		TOTAL			158	163	96.93
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	9.283m	5.160ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			570	585	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.97	99.61	95.53	99.70	93.55	92.82	100.00	98.83	98.32

Failure Buckets

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 4 failures:

Test otbn_sec_cm has 4 failures.

1.otbn_sec_cm.55446206792189929337275795945240403245880067988033168414256130180543566017214
Line 105, in log /workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 62922366 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 62922366 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 62922366 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 62922366 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 62922366 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

2.otbn_sec_cm.27753527672032062934484904371137106743329632762385810126431573423118059029476
Line 148, in log /workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 159161180 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 159161180 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 159161180 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 159161180 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 159161180 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 2 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

7.otbn_escalate.83613369868914003636695896629949386680004482878013414185552659957629034491035
Line 100, in log /workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 92938564 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  92938564 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  92938564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.otbn_escalate.1567069371395003069881866983583816789638919025831501011131832435076343329068
Line 92, in log /workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/30.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 158860734 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 158860734 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 158860734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 1.otbn_stress_all_with_rand_reset.41675656226711508290596213136751539520233708771670834785201951884041523951421
    Line 329, in log /workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1651270311 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1651270311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stress_all_with_rand_reset.80407990017628218897800377601437816114144543937325618914193559923308869172061
    Line 157, in log /workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 148707050 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 148707050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.36054460294113387800637976248507304171641861406259228270369738269970967346720
    Line 245, in log /workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1046920247 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1046920247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.34357896211000957873620847065607801869651426170727613061989977758106478619456
    Line 560, in log /workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 937391019 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 937391019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 9.otbn_partial_wipe.80392566990020450012892809118685421329106421494936724614187616695637193421790
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/9.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 3339980 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3339980 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3339980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 19.otbn_escalate.29569301414778344205511049067305176296753105727367857831572144202326600795698
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_08_26/otbn-sim-xcelium/19.otbn_escalate/latest/run.log
```
  UVM_ERROR @   2093671 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   2093671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```