OTBN Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Simulator: XCELIUM

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	16.000s	73.663us	1	1	100.00
V1	single_binary	otbn_single	2.600m	1.692ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	43.234us	5	5	100.00
V1	csr_rw	otbn_csr_rw	11.000s	27.588us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	14.000s	903.509us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	46.805us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	18.000s	52.962us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	11.000s	27.588us	20	20	100.00
		otbn_csr_aliasing	8.000s	46.805us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.183m	3.552ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	29.000s	1.384ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.300m	214.668us	10	10	100.00
V2	multi_error	otbn_multi_err	1.133m	1.466ms	1	1	100.00
V2	back_to_back	otbn_multi	2.867m	1.032ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.833m	575.709us	10	10	100.00
V2	lc_escalation	otbn_escalate	26.000s	46.875us	56	60	93.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	58.850us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	25.000s	53.682us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	19.316us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	45.134us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	19.000s	227.665us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	19.000s	227.665us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	43.234us	5	5	100.00
		otbn_csr_rw	11.000s	27.588us	20	20	100.00
		otbn_csr_aliasing	8.000s	46.805us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	24.748us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	43.234us	5	5	100.00
		otbn_csr_rw	11.000s	27.588us	20	20	100.00
		otbn_csr_aliasing	8.000s	46.805us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	24.748us	20	20	100.00
V2		TOTAL			242	246	98.37
V2S	mem_integrity	otbn_imem_err	16.000s	71.353us	10	10	100.00
		otbn_dmem_err	16.000s	71.997us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	15.000s	218.767us	5	5	100.00
		otbn_controller_ispr_rdata_err	1.450m	237.002us	5	5	100.00
		otbn_mac_bignum_acc_err	18.000s	35.831us	5	5	100.00
		otbn_urnd_err	8.000s	16.478us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	100.402us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	12.000s	37.916us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	26.780us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	10.533m	2.213ms	3	5	60.00
		otbn_tl_intg_err	2.467m	590.906us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.017m	185.323us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	16.000s	73.663us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	71.997us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	71.353us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	2.467m	590.906us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	26.000s	46.875us	56	60	93.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	71.353us	10	10	100.00
		otbn_dmem_err	16.000s	71.997us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	58.850us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	100.402us	5	5	100.00
		otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.600m	1.692ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	71.353us	10	10	100.00
		otbn_dmem_err	16.000s	71.997us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	58.850us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	100.402us	5	5	100.00
		otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	26.000s	46.875us	56	60	93.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	71.353us	10	10	100.00
		otbn_dmem_err	16.000s	71.997us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	58.850us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	100.402us	5	5	100.00
		otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.600m	1.692ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	27.659us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	27.000s	69.145us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.017m	342.530us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.017m	342.530us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	29.395us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	44.000s	124.487us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	161.880us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	161.880us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	28.000s	44.989us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.600m	1.692ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.600m	1.692ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.600m	1.692ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.867m	1.032ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.600m	1.692ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.600m	1.692ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	15.000s	196.275us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.600m	1.692ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	10.533m	2.213ms	3	5	60.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	10.067m	2.094ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			572	585	97.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.96	99.60	95.40	99.70	93.49	92.80	100.00	98.37	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test otbn_stress_all_with_rand_reset has 4 failures.
  - 2.otbn_stress_all_with_rand_reset.91389098005511547701638192834743395857344983488192599691028163851611179579800
    Line 244, in log /workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3718907302 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3718907302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otbn_stress_all_with_rand_reset.18452121374653278181895027995473642952199247085843496863501819126786776925107
    Line 399, in log /workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 700285193 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 700285193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

14.otbn_escalate.31097646387132696574444582861016727300248133850796922050679871154110774454182
Line 103, in log /workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/14.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16663252 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  16663252 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  16663252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.otbn_escalate.51164520624216122670699437530129494453706372734030357612816682745681668152239
Line 91, in log /workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/24.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 7716719 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   7716719 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   7716719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.108349245697734041161481622571658758288530221004718896568946428249382891931851
Line 128, in log /workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 107453674 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 107453674 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 107453674 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 107453674 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 107453674 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

4.otbn_sec_cm.28842978150113387422870900001409498637300892045882848751014740392385794102540
Line 128, in log /workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 257150601 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 257150601 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 257150601 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 257150601 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 257150601 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.21472852247653418835000265752756379274672679003815931495655061561163388889591
    Line 350, in log /workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 502514539 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 502514539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.92974126962654178988538594095150348612947136412926261897679954952362352387785
    Line 300, in log /workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1230203981 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1230203981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 9.otbn_partial_wipe.110432875079867828517811564912157194146479411827030627667120934765243897485973
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/9.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 6657569 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   6657569 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   6657569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```