OTBN Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Simulator: XCELIUM

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	19.000s	138.678us	1	1	100.00
V1	single_binary	otbn_single	2.983m	464.692us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	11.000s	29.551us	5	5	100.00
V1	csr_rw	otbn_csr_rw	23.000s	37.872us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	89.811us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	94.788us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	24.000s	217.132us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	23.000s	37.872us	20	20	100.00
		otbn_csr_aliasing	7.000s	94.788us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.050m	4.760ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	36.000s	5.495ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.133m	131.246us	10	10	100.00
V2	multi_error	otbn_multi_err	1.650m	263.279us	1	1	100.00
V2	back_to_back	otbn_multi	7.850m	1.265ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.700m	284.230us	10	10	100.00
V2	lc_escalation	otbn_escalate	27.000s	51.711us	56	60	93.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	45.433us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	33.000s	206.446us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	21.271us	50	50	100.00
V2	intr_test	otbn_intr_test	32.000s	49.438us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	29.000s	205.756us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	29.000s	205.756us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	11.000s	29.551us	5	5	100.00
		otbn_csr_rw	23.000s	37.872us	20	20	100.00
		otbn_csr_aliasing	7.000s	94.788us	5	5	100.00
		otbn_same_csr_outstanding	21.000s	16.853us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	11.000s	29.551us	5	5	100.00
		otbn_csr_rw	23.000s	37.872us	20	20	100.00
		otbn_csr_aliasing	7.000s	94.788us	5	5	100.00
		otbn_same_csr_outstanding	21.000s	16.853us	20	20	100.00
V2		TOTAL			242	246	98.37
V2S	mem_integrity	otbn_imem_err	18.000s	56.085us	10	10	100.00
		otbn_dmem_err	21.000s	41.283us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	100.549us	5	5	100.00
		otbn_controller_ispr_rdata_err	14.000s	23.576us	5	5	100.00
		otbn_mac_bignum_acc_err	17.000s	27.469us	5	5	100.00
		otbn_urnd_err	15.000s	66.913us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	17.000s	48.612us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	10.349us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	13.000s	60.849us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	11.250m	5.324ms	3	5	60.00
		otbn_tl_intg_err	1.133m	298.774us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	59.000s	222.515us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	19.000s	138.678us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	21.000s	41.283us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	18.000s	56.085us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.133m	298.774us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	27.000s	51.711us	56	60	93.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	18.000s	56.085us	10	10	100.00
		otbn_dmem_err	21.000s	41.283us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	45.433us	5	5	100.00
		otbn_illegal_mem_acc	17.000s	48.612us	5	5	100.00
		otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.983m	464.692us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	18.000s	56.085us	10	10	100.00
		otbn_dmem_err	21.000s	41.283us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	45.433us	5	5	100.00
		otbn_illegal_mem_acc	17.000s	48.612us	5	5	100.00
		otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	27.000s	51.711us	56	60	93.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	18.000s	56.085us	10	10	100.00
		otbn_dmem_err	21.000s	41.283us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	45.433us	5	5	100.00
		otbn_illegal_mem_acc	17.000s	48.612us	5	5	100.00
		otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.983m	464.692us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	18.000s	44.426us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	16.000s	34.268us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.250m	219.958us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.250m	219.958us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	17.000s	75.383us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	3.967m	619.599us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	15.000s	204.107us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	15.000s	204.107us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	20.000s	106.944us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.983m	464.692us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.983m	464.692us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.983m	464.692us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	7.850m	1.265ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.983m	464.692us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.983m	464.692us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	84.184us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.983m	464.692us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	11.250m	5.324ms	3	5	60.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	10.367m	3.208ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			573	585	97.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.97	99.61	95.53	99.70	93.67	92.82	100.00	98.60	99.16

Failure Buckets

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

21.otbn_escalate.33033058288449115962424810847987911898713690354210937533625546792309248985506
Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/21.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23937099 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  23937099 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  23937099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.otbn_escalate.77128833352656572461660676262239919538010357409553826182215788260193756370645
Line 101, in log /workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/42.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 28245881 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  28245881 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  28245881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.88980471950577489668445766607524259632604330742318515172275440252080878283780
    Line 191, in log /workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2558583632 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2558583632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otbn_stress_all_with_rand_reset.103067240434189105851851190027769600835466817734697202407297981014399174736425
    Line 280, in log /workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2332518027 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2332518027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.24146006917264296044254524705610894536081375118210384137452278778200656866889
Line 77, in log /workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 2021738 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 2021738 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 2021738 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 2021738 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 2021738 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

3.otbn_sec_cm.111050144365045937122661493624196073059989719920716274081698186402852542542997
Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 29354601 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 29354601 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 29354601 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 29354601 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 29354601 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 7.otbn_stress_all_with_rand_reset.9994334045444351474771046370582016987149411222854303029348041046259144269152
    Line 141, in log /workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  30093208 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  30093208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otbn_stress_all_with_rand_reset.448366160336601497415673303150709765683487823503376497939534973458972397670
    Line 245, in log /workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2864213168 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2864213168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 6.otbn_rf_base_intg_err.9692447957256755392424061390033164291789045886984672621271358126883123317973
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  32702942 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
  UVM_INFO @  32702942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 8.otbn_partial_wipe.99958757204207777382296164595112612381988550232513368002648507804694251518672
    Line 94, in log /workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 3253878 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
  UVM_ERROR @   3253878 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
  UVM_INFO @   3253878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 35.otbn_escalate.40781178851307189710458525733827802301069428074973446069657899785201195422760
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_31/otbn-sim-xcelium/35.otbn_escalate/latest/run.log
```
  UVM_ERROR @   9504053 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   9504053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```