OTBN Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Simulator: XCELIUM

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	16.000s	551.752us	1	1	100.00
V1	single_binary	otbn_single	2.683m	508.066us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	22.246us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	19.759us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	355.599us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	10.000s	25.412us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	40.242us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	19.759us	20	20	100.00
		otbn_csr_aliasing	10.000s	25.412us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.067m	1.866ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	34.000s	8.812ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.550m	293.928us	10	10	100.00
V2	multi_error	otbn_multi_err	2.100m	398.268us	1	1	100.00
V2	back_to_back	otbn_multi	3.483m	708.939us	10	10	100.00
V2	stress_all	otbn_stress_all	6.800m	1.287ms	10	10	100.00
V2	lc_escalation	otbn_escalate	52.000s	149.880us	54	60	90.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	28.917us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	22.000s	146.875us	10	10	100.00
V2	alert_test	otbn_alert_test	12.000s	27.448us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	45.545us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	13.000s	63.104us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	13.000s	63.104us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	22.246us	5	5	100.00
		otbn_csr_rw	7.000s	19.759us	20	20	100.00
		otbn_csr_aliasing	10.000s	25.412us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	24.396us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	22.246us	5	5	100.00
		otbn_csr_rw	7.000s	19.759us	20	20	100.00
		otbn_csr_aliasing	10.000s	25.412us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	24.396us	20	20	100.00
V2		TOTAL			240	246	97.56
V2S	mem_integrity	otbn_imem_err	15.000s	36.881us	10	10	100.00
		otbn_dmem_err	3.250m	611.260us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	25.000s	572.552us	5	5	100.00
		otbn_controller_ispr_rdata_err	13.000s	17.306us	5	5	100.00
		otbn_mac_bignum_acc_err	16.000s	43.075us	5	5	100.00
		otbn_urnd_err	8.000s	46.278us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	25.066us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	12.313us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	86.532us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	8.567m	17.848ms	3	5	60.00
		otbn_tl_intg_err	47.000s	204.219us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.033m	258.781us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	16.000s	551.752us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	3.250m	611.260us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	36.881us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	47.000s	204.219us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	52.000s	149.880us	54	60	90.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	36.881us	10	10	100.00
		otbn_dmem_err	3.250m	611.260us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	28.917us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	25.066us	5	5	100.00
		otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.683m	508.066us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	36.881us	10	10	100.00
		otbn_dmem_err	3.250m	611.260us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	28.917us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	25.066us	5	5	100.00
		otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	52.000s	149.880us	54	60	90.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	36.881us	10	10	100.00
		otbn_dmem_err	3.250m	611.260us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	28.917us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	25.066us	5	5	100.00
		otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.683m	508.066us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	19.000s	46.791us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	12.000s	89.914us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.217m	301.943us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.217m	301.943us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	19.000s	28.439us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	67.257us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	22.878us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	22.878us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	28.000s	62.531us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.683m	508.066us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.683m	508.066us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.683m	508.066us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.483m	708.939us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.683m	508.066us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.683m	508.066us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	15.000s	121.810us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.683m	508.066us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.567m	17.848ms	3	5	60.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	8.383m	1.614ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			570	585	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.95	99.60	95.40	99.70	93.44	92.72	100.00	98.37	99.16

Failure Buckets

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 6 failures:

Test otbn_escalate has 6 failures.

8.otbn_escalate.54650959566849952234275475446221328027222023954532152567405016702931238405250
Line 94, in log /workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 29152075 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  29152075 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  29152075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.otbn_escalate.90915046237923532387844954280882600788894619078889409406602555697295658591097
Line 96, in log /workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 36884439 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  36884439 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  36884439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test otbn_stress_all_with_rand_reset has 4 failures.
  - 2.otbn_stress_all_with_rand_reset.38996878185377786770282504226140530480297139927892231452904495550330656311084
    Line 142, in log /workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 939468763 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 939468763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stress_all_with_rand_reset.56068885706400704715416556961047875612400472496937498115060547747415385197274
    Line 150, in log /workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 901525449 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 901525449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 2 failures:

Test otbn_partial_wipe has 2 failures.

1.otbn_partial_wipe.63511663031820090880075895020825709625972136068679339698683221465168680257472
Line 91, in log /workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/1.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 11756149 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  11756149 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  11756149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.otbn_partial_wipe.82104158736496394295284448932867544575164658858292387208122379555706241975688
Line 94, in log /workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/6.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 14420782 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  14420782 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  14420782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.37618471328256924050358107761254604137532108363793273202292523420173381758526
Line 96, in log /workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 82427904 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 82427904 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 82427904 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 82427904 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 82427904 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

3.otbn_sec_cm.14631614242354236588880970021420613306377728151947383240192878431436248473279
Line 135, in log /workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 68333405 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 68333405 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 68333405 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 68333405 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 68333405 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.29011712821542789477435910477903980681466517270736561704389403209486927435026
    Line 302, in log /workspaces/repo/scratch/os_regression_2024_09_03/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 907105847 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 907105847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```