OTBN Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Simulator: XCELIUM

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	65.726us	1	1	100.00
V1	single_binary	otbn_single	1.217m	31.472us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	1.283m	38.592us	5	5	100.00
V1	csr_rw	otbn_csr_rw	59.000s	34.270us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	59.000s	24.939us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	27.000s	41.717us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	1.150m	57.372us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	59.000s	34.270us	20	20	100.00
		otbn_csr_aliasing	27.000s	41.717us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.067m	4.911ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	1.250m	733.882us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.817m	99.536us	10	10	100.00
V2	multi_error	otbn_multi_err	2.150m	509.426us	1	1	100.00
V2	back_to_back	otbn_multi	2.300m	567.018us	10	10	100.00
V2	stress_all	otbn_stress_all	3.217m	508.386us	10	10	100.00
V2	lc_escalation	otbn_escalate	1.183m	29.884us	55	60	91.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	1.083m	110.129us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	1.100m	170.455us	10	10	100.00
V2	alert_test	otbn_alert_test	51.000s	18.924us	50	50	100.00
V2	intr_test	otbn_intr_test	48.000s	57.234us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	1.217m	1.706ms	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	1.217m	1.706ms	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	1.283m	38.592us	5	5	100.00
		otbn_csr_rw	59.000s	34.270us	20	20	100.00
		otbn_csr_aliasing	27.000s	41.717us	5	5	100.00
		otbn_same_csr_outstanding	52.000s	70.679us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	1.283m	38.592us	5	5	100.00
		otbn_csr_rw	59.000s	34.270us	20	20	100.00
		otbn_csr_aliasing	27.000s	41.717us	5	5	100.00
		otbn_same_csr_outstanding	52.000s	70.679us	20	20	100.00
V2		TOTAL			241	246	97.97
V2S	mem_integrity	otbn_imem_err	1.150m	36.020us	10	10	100.00
		otbn_dmem_err	1.117m	27.589us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	1.083m	109.891us	5	5	100.00
		otbn_controller_ispr_rdata_err	1.067m	57.307us	5	5	100.00
		otbn_mac_bignum_acc_err	1.067m	57.028us	5	5	100.00
		otbn_urnd_err	30.000s	17.278us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	1.083m	96.135us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	15.000s	28.969us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	1.217m	45.979us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	7.917m	13.466ms	2	5	40.00
		otbn_tl_intg_err	1.367m	190.596us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.650m	375.929us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	65.726us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	1.117m	27.589us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	1.150m	36.020us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.367m	190.596us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.183m	29.884us	55	60	91.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	1.150m	36.020us	10	10	100.00
		otbn_dmem_err	1.117m	27.589us	15	15	100.00
		otbn_zero_state_err_urnd	1.083m	110.129us	5	5	100.00
		otbn_illegal_mem_acc	1.083m	96.135us	5	5	100.00
		otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.217m	31.472us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	1.150m	36.020us	10	10	100.00
		otbn_dmem_err	1.117m	27.589us	15	15	100.00
		otbn_zero_state_err_urnd	1.083m	110.129us	5	5	100.00
		otbn_illegal_mem_acc	1.083m	96.135us	5	5	100.00
		otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.183m	29.884us	55	60	91.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	1.150m	36.020us	10	10	100.00
		otbn_dmem_err	1.117m	27.589us	15	15	100.00
		otbn_zero_state_err_urnd	1.083m	110.129us	5	5	100.00
		otbn_illegal_mem_acc	1.083m	96.135us	5	5	100.00
		otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.217m	31.472us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	1.200m	4.202us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	1.217m	48.668us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.800m	504.318us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.800m	504.318us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	1.917m	2.013ms	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	1.050m	197.341us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.383m	38.712us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.383m	38.712us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	1.283m	106.929us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.217m	31.472us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.217m	31.472us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.217m	31.472us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.300m	567.018us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.217m	31.472us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.217m	31.472us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	1.267m	23.315us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.217m	31.472us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.917m	13.466ms	2	5	40.00
V2S		TOTAL			157	163	96.32
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	16.900m	2.747ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			567	585	96.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	16	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	99.60	95.31	99.69	93.52	92.64	97.44	91.02	98.74

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test otbn_stress_all_with_rand_reset has 5 failures.
  - 0.otbn_stress_all_with_rand_reset.109343037399958070186772428497513884749992295096193254246245558188074714720869
    Line 249, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1069244132 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1069244132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stress_all_with_rand_reset.80666863309581585574501816598655542192967955169718166752647894325737911234335
    Line 193, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2368263048 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2368263048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

24.otbn_escalate.67687192763864600636892068927684361823665163689393555223452059985776470763666
Line 96, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/24.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12673472 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  12673472 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  12673472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.otbn_escalate.101975550052179919468829494938367311605471526580233715982221668093485143053207
Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/31.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 123808653 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 123808653 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 123808653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.61962309098740420659268441660329380421161459622189130463136281532948354321924
Line 103, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 39263221 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 39263221 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 39263221 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 39263221 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 39263221 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.115744252891286994457527628111637863619565763103184553265653976947050888111580
Line 94, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 40383145 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 40383145 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 40383145 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 40383145 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 40383145 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 6.otbn_stress_all_with_rand_reset.34480449112899901860812104263244904285822257861310586296257351709211367571322
    Line 147, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 594334531 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 594334531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otbn_stress_all_with_rand_reset.43746515905164387710237138295765081332517596801888069943811074971907459908263
    Line 246, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1071471967 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1071471967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 2.otbn_partial_wipe.108107806630656368037269732625336998653699411853329255785632127831114788195928
    Line 100, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 6582487 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   6582487 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   6582487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,969): Assertion OnlyWriteLoadDataBignumWhenDMemValid_A has failed has 1 failures:

Test otbn_ctrl_redun has 1 failures.

3.otbn_ctrl_redun.54806212541579203336992385993046323839437283848954901174414160621171052108782
Line 93, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,969): (time 4202212 PS) Assertion tb.dut.u_otbn_core.OnlyWriteLoadDataBignumWhenDMemValid_A has failed
  UVM_ERROR @   4202212 ps: (otbn_core.sv:969) [ASSERT FAILED] OnlyWriteLoadDataBignumWhenDMemValid_A
  UVM_INFO @   4202212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 5.otbn_rf_base_intg_err.114437328542004208286185840614071848886986055227820122812458162505103669363075
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/5.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 2012944207 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x8d570018)
  UVM_INFO @ 2012944207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 28.otbn_escalate.2192006147343036343454187453219928054192104412729474351675834704226788816860
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_09_08/otbn-sim-xcelium/28.otbn_escalate/latest/run.log
```
  UVM_FATAL @  42962617 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @  42962617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```