OTP_CTRL Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: 83db9403d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.940s	990.443us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.090s	4.283ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.740s	1.461ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.930s	543.325us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	15.520s	6.900ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.430s	2.010ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.800s	412.974us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.930s	543.325us	20	20	100.00
		otp_ctrl_csr_aliasing	6.430s	2.010ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.410s	121.086us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.740s	515.326us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	16.780s	609.957us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.080s	2.489ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	34.310s	14.130ms	10	10	100.00
		otp_ctrl_check_fail	31.630s	12.567ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	9.690s	4.593ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	27.090s	5.380ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	48.240s	2.149ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	26.940s	12.876ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	25.370s	8.203ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	41.520s	20.562ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.375m	13.731ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	3.807m	29.480ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.050s	538.221us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.140s	1.061ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.230s	158.226us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.230s	158.226us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.740s	1.461ms	5	5	100.00
		otp_ctrl_csr_rw	1.930s	543.325us	20	20	100.00
		otp_ctrl_csr_aliasing	6.430s	2.010ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.750s	1.929ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.740s	1.461ms	5	5	100.00
		otp_ctrl_csr_rw	1.930s	543.325us	20	20	100.00
		otp_ctrl_csr_aliasing	6.430s	2.010ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.750s	1.929ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
		otp_ctrl_tl_intg_err	19.210s	4.766ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	19.210s	4.766ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.090s	4.283ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.090s	4.283ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
		otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
		otp_ctrl_macro_errs	41.520s	20.562ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
		otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
		otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
		otp_ctrl_macro_errs	41.520s	20.562ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.340s	2.043ms	200	200	100.00
		otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.080s	2.489ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	31.630s	12.567ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	27.090s	5.380ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	27.090s	5.380ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	27.090s	5.380ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	27.090s	5.380ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	27.090s	5.380ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.090s	4.283ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	27.090s	5.380ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.090s	4.283ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.832m	130.990ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	9.690s	4.593ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.090s	4.283ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.090s	4.283ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	41.520s	20.562ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	11.790s	3.028ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.996h	8.614s	94	100	94.00
V3		TOTAL			95	101	94.06
		TOTAL			1337	1343	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.24	92.63	91.61	92.25	90.99	93.45	96.53	95.19

Failure Buckets

• Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

    • 4.otp_ctrl_stress_all_with_rand_reset.2745677757
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:2d2ebb9e-6208-413d-af9f-d4123e107351
      

    • 5.otp_ctrl_stress_all_with_rand_reset.3349222775
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:06003fae-b92b-491f-bb0e-dc597b696799
      

    • ... and 2 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:619) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpOperationDone has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 64.otp_ctrl_stress_all_with_rand_reset.910015415
      Line 1026, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 208438677824 ps: (otp_ctrl_scoreboard.sv:619) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpOperationDone
        UVM_INFO @ 208438677824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 79.otp_ctrl_stress_all_with_rand_reset.107985833
      Line 1835, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1691600491141 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 1691600491141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.22_19.39.09
• 2023.05.21_20.15.38
• 2023.05.20_19.32.03
• 2023.05.19_16.13.05
• 2023.05.18_19.15.40
• 2023.05.17_17.59.32
• 2023.05.16_19.23.36