OTP_CTRL Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: 94eb0df12

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.170s	927.341us	1	1	100.00
V1	smoke	otp_ctrl_smoke	10.470s	4.517ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.290s	962.609us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.920s	536.058us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	15.970s	5.564ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.380s	482.861us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.370s	105.468us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.920s	536.058us	20	20	100.00
		otp_ctrl_csr_aliasing	4.380s	482.861us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.390s	126.778us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.460s	134.335us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	15.420s	608.909us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.140s	2.505ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	16.770s	839.410us	10	10	100.00
		otp_ctrl_check_fail	43.490s	14.923ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	10.850s	3.476ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	35.190s	16.404ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	38.120s	2.127ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	24.380s	10.620ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	25.660s	8.801ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	38.810s	3.191ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	3.564m	30.243ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	4.438m	83.041ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.920s	548.328us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.670s	322.028us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.340s	1.038ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.340s	1.038ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.290s	962.609us	5	5	100.00
		otp_ctrl_csr_rw	1.920s	536.058us	20	20	100.00
		otp_ctrl_csr_aliasing	4.380s	482.861us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.080s	367.828us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.290s	962.609us	5	5	100.00
		otp_ctrl_csr_rw	1.920s	536.058us	20	20	100.00
		otp_ctrl_csr_aliasing	4.380s	482.861us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.080s	367.828us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
		otp_ctrl_tl_intg_err	30.900s	19.202ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	30.900s	19.202ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	10.470s	4.517ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	10.470s	4.517ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
		otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
		otp_ctrl_macro_errs	38.810s	3.191ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
		otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
		otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
		otp_ctrl_macro_errs	38.810s	3.191ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	10.610s	979.477us	200	200	100.00
		otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.140s	2.505ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	43.490s	14.923ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	35.190s	16.404ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	35.190s	16.404ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	35.190s	16.404ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	35.190s	16.404ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	35.190s	16.404ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	10.470s	4.517ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	35.190s	16.404ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	10.470s	4.517ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	2.597m	31.475ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	10.850s	3.476ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	10.470s	4.517ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	10.470s	4.517ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	38.810s	3.191ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.620s	3.014ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.987h	783.919ms	93	100	93.00
V3		TOTAL			94	101	93.07
		TOTAL			1336	1343	99.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.57	92.63	91.69	92.71	92.68	93.45	96.53	95.27

Failure Buckets

• Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 5 failures.

    • 4.otp_ctrl_stress_all_with_rand_reset.2258047035
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:92f8b10c-f28f-4e2b-bbbb-1c89f254302c
      

    • 12.otp_ctrl_stress_all_with_rand_reset.1729599858
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:5c8c3525-1455-4c2b-bec5-8237c842618a
      

    • ... and 3 more failures.

• UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 2 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 79.otp_ctrl_stress_all_with_rand_reset.539424569
      Line 251, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 249188819 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 249188819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 89.otp_ctrl_stress_all_with_rand_reset.1752820392
      Line 600, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 246436324991 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 246436324991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.24_17.34.11
• 2023.05.23_17.52.18
• 2023.05.22_19.39.09
• 2023.05.21_20.15.38
• 2023.05.20_19.32.03
• 2023.05.19_16.13.05
• 2023.05.18_19.15.40