OTP_CTRL Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.640s	81.428us	1	1	100.00
V1	smoke	otp_ctrl_smoke	13.090s	1.280ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.040s	1.382ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.160s	585.576us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.250s	437.864us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	3.850s	931.536us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.140s	1.716ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.160s	585.576us	20	20	100.00
		otp_ctrl_csr_aliasing	3.850s	931.536us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.320s	43.819us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.320s	40.745us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.000s	722.806us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.720s	2.483ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	21.750s	842.457us	10	10	100.00
		otp_ctrl_check_fail	1.196m	34.615ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	10.600s	1.309ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	51.730s	10.882ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	26.900s	1.632ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	28.600s	11.093ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	17.310s	6.195ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	39.590s	14.926ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.252m	9.019ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.687m	53.241ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	1.890s	523.342us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.940s	509.601us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.860s	2.536ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.860s	2.536ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.040s	1.382ms	5	5	100.00
		otp_ctrl_csr_rw	2.160s	585.576us	20	20	100.00
		otp_ctrl_csr_aliasing	3.850s	931.536us	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.990s	243.738us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.040s	1.382ms	5	5	100.00
		otp_ctrl_csr_rw	2.160s	585.576us	20	20	100.00
		otp_ctrl_csr_aliasing	3.850s	931.536us	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.990s	243.738us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
		otp_ctrl_tl_intg_err	37.170s	18.991ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	37.170s	18.991ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	13.090s	1.280ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	13.090s	1.280ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
		otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
		otp_ctrl_macro_errs	39.590s	14.926ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
		otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
		otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
		otp_ctrl_macro_errs	39.590s	14.926ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.810s	5.106ms	200	200	100.00
		otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.720s	2.483ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.196m	34.615ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	51.730s	10.882ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	51.730s	10.882ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	51.730s	10.882ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	51.730s	10.882ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	51.730s	10.882ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	13.090s	1.280ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	51.730s	10.882ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	13.090s	1.280ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	2.742m	34.699ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	10.600s	1.309ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	13.090s	1.280ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	13.090s	1.280ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	39.590s	14.926ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	15.450s	7.385ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.987h	4.387s	95	100	95.00
V3		TOTAL			96	101	95.05
		TOTAL			1336	1343	99.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.35	92.59	91.24	92.10	92.39	93.29	96.53	95.27

Failure Buckets

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 49.otp_ctrl_stress_all_with_rand_reset.1177041170
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:be4de7ce-d00d-4ee5-b712-13d2b930917c
```
  - 59.otp_ctrl_stress_all_with_rand_reset.4111468992
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:94314ea7-5bda-4e3d-906e-9699a3d665bf
```
  - ... and 1 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 4.otp_ctrl_csr_mem_rw_with_rand_reset.3590662402
    Line 251, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 113816172 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 113816172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 71.otp_ctrl_stress_all_with_rand_reset.2922002354
    Line 1234, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 454043673893 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 454043673893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1347) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@219698) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

16.otp_ctrl_stress_all.6258727
Line 266, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 12074824204 ps: (otp_ctrl_scoreboard.sv:1347) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@219698) { a_addr: 'hac0767b4  a_data: 'h92b90652  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb6  a_opcode: 'h0  a_user: 'h27474  d_param: 'h0  d_source: 'hb6  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 12074824204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 67.otp_ctrl_stress_all_with_rand_reset.3046838937
    Line 342, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24573385834 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 24573385834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```