PWM Simulation Results

Wednesday January 10 2024 20:03:22 UTC

GitHub Revision: `cf38c1d296`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 55803132295021657086212552594002090640066687299415498461130788370399872772386

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	10.000s	535.148us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	28.149us	5	5	100.00
V1	csr_rw	pwm_csr_rw	7.000s	92.530us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	11.000s	4.949ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	535.406us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	29.045us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	7.000s	92.530us	20	20	100.00
		pwm_csr_aliasing	4.000s	535.406us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.083m	10.610ms	49	50	98.00
V2	pulse	pwm_rand_output	1.083m	10.610ms	49	50	98.00
V2	blink	pwm_rand_output	1.083m	10.610ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.083m	10.610ms	49	50	98.00
V2	resolution	pwm_rand_output	1.083m	10.610ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.083m	10.610ms	49	50	98.00
V2	polarity	pwm_rand_output	1.083m	10.610ms	49	50	98.00
V2	phase	pwm_rand_output	1.083m	10.610ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.083m	10.610ms	49	50	98.00
V2	perf	pwm_perf	57.000s	43.751ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.533m	64.288ms	48	50	96.00
V2	alert_test	pwm_alert_test	7.000s	48.842us	50	50	100.00
V2	intr_test	pwm_intr_test	8.000s	82.466us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	7.000s	302.089us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	7.000s	302.089us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	28.149us	5	5	100.00
		pwm_csr_rw	7.000s	92.530us	20	20	100.00
		pwm_csr_aliasing	4.000s	535.406us	5	5	100.00
		pwm_same_csr_outstanding	5.000s	117.510us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	28.149us	5	5	100.00
		pwm_csr_rw	7.000s	92.530us	20	20	100.00
		pwm_csr_aliasing	4.000s	535.406us	5	5	100.00
		pwm_same_csr_outstanding	5.000s	117.510us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	6.000s	62.015us	20	20	100.00
		pwm_sec_cm	3.000s	74.969us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	6.000s	62.015us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	99.38	98.89	99.68	95.00	94.92	--	100.00	99.34

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

6.pwm_stress_all.21154987043169554679188080975507326216415294334462728125269442143866819441595
Line 16828, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/6.pwm_stress_all/latest/run.log

  UVM_ERROR @ 43821460858 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [2] did not MATCH
  UVM_INFO @ 43821460858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.pwm_stress_all.56630453158704087538170857266598944678371084860022047740821429528312853314156
Line 767, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/25.pwm_stress_all/latest/run.log

  UVM_ERROR @ 91709585710 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 91709585710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_rand_output has 1 failures.
  - 35.pwm_rand_output.43972570089236247640366042136115114952912794805221544953768835293060062188256
    Line 1119, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/35.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```