PWM Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 11.000s 4.243ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 155.371us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 29.465us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 10.000s 669.468us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 647.590us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 8.000s 31.548us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 29.465us 20 20 100.00
pwm_csr_aliasing 4.000s 647.590us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 5.400m 10.943ms 50 50 100.00
V2 pulse pwm_rand_output 5.400m 10.943ms 50 50 100.00
V2 blink pwm_rand_output 5.400m 10.943ms 50 50 100.00
V2 heartbeat pwm_rand_output 5.400m 10.943ms 50 50 100.00
V2 resolution pwm_rand_output 5.400m 10.943ms 50 50 100.00
V2 multi_channel pwm_rand_output 5.400m 10.943ms 50 50 100.00
V2 polarity pwm_rand_output 5.400m 10.943ms 50 50 100.00
V2 phase pwm_rand_output 5.400m 10.943ms 50 50 100.00
V2 lowpower pwm_rand_output 5.400m 10.943ms 50 50 100.00
V2 perf pwm_perf 54.000s 41.998ms 50 50 100.00
V2 stress_all pwm_stress_all 4.117m 114.938ms 49 50 98.00
V2 alert_test pwm_alert_test 8.000s 24.656us 50 50 100.00
V2 intr_test pwm_intr_test 7.000s 24.345us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 5.000s 477.483us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 5.000s 477.483us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 155.371us 5 5 100.00
pwm_csr_rw 3.000s 29.465us 20 20 100.00
pwm_csr_aliasing 4.000s 647.590us 5 5 100.00
pwm_same_csr_outstanding 4.000s 62.518us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 155.371us 5 5 100.00
pwm_csr_rw 3.000s 29.465us 20 20 100.00
pwm_csr_aliasing 4.000s 647.590us 5 5 100.00
pwm_same_csr_outstanding 4.000s 62.518us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 5.000s 1.281ms 20 20 100.00
pwm_sec_cm 3.000s 266.094us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 5.000s 1.281ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.66 99.66 99.38 100.00 95.24 94.92 -- 100.00 99.34

Failure Buckets

Past Results